R5F5631BDDFP Renesas Electronics Corporation., R5F5631BDDFP Datasheet
R5F5631BDDFP
Manufacturer Part Number
R5F5631BDDFP
Description
LQFP 100
Manufacturer
Renesas Electronics Corporation.
Datasheets
1.R5F5631ACDLK.pdf
(101 pages)
2.R5F5631BDDFP.pdf
(108 pages)
3.R5F5631BDDFP.pdf
(108 pages)
Specifications of R5F5631BDDFP
Pack_quantity
1
Comm_code
85423190
Lead_time
126
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F5631BDDFP#V0
Manufacturer:
XILINX
Quantity:
224
Company:
Part Number:
R5F5631BDDFP#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
RX63N Group, RX631 Group
Renesas MCUs
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, up to 2-MB flash
memory, Ethernet MAC, full-speed USB 2.0 host/function/OTG interface,
various communications interfaces including CAN, 10- & 12-bit A/D
converters, RTC
R01DS0098EJ0090 Rev.0.90
Dec 27, 2011
Features
RX63N Group products incorporate an Ethernet controller while
RX631 Group products do not.
■ 32-bit RX CPU core
■ Low-power design and architecture
■ On-chip main flash memory, no wait states
■ On-chip data flash memory
■ On-chip SRAM, no wait states
■ DMA
■ Reset and supply management
■ Clock functions
■ Real-time clock
■ Independent watchdog timer
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating point
Two types of multiply-and-accumulation unit (between memories and
32-bit multiplier (fastest instruction execution takes one CPU clock cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
JTAG and FINE (two-line) debugging interfaces
Operation from a single 2.7- to 3.6-V supply
Low power consumption: A product that supports all peripheral functions
RTC is capable of operation from a dedicated power supply (min. operating
Four low-power modes
Supports ROM-less versions and versions with up to 2 Mbytes of ROM
100-MHz operation, 10-ns read cycle (no wait states)
384-Kbyte to 2-Mbyte capacities
User code programmable via the USB, SCI, or JTAG
ROM-less or 32 Kbytes of ROM (reprogrammable up to 100,000 times)
Programming/erasing as background operations (BGOs)
32- to 128-Kbyte capacities
For instructions and operands
Can provide backup on deep software standby
DMAC: Four channels
DTC
EXDMAC: Two channels
Dedicated DMAC for the Ethernet controller: Single channel
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
External crystal oscillator or internal PLL for operation at 4 to 16 MHz
Internal 125-kHz LOCO and 50-MHz HOCO
Dedicated 125-kHz LOCO for the IWDT
Adjustment functions (30 seconds, leap year, and error)
Time capture function
125-kHz LOCO clock operation
between registers)
draws only 500 μA/MHz.
voltage: 2 V).
(ROM-less version: RX631 Group only)
(for capturing times in response to event-signal input on external pins)
Specifications in this document are tentative and subject to change.
■ Useful functions for IEC60730 compliance
■ Various communications interfaces
■ External address space
■ Up to 20 extended-function timers
■ A/D converter for 1-MHz Operation
■ 10-bit D/A converter: 2 channels
■ Temperature sensor for measuring temperature within
■ Register write protection can protect values in
■ Up to 134 pins for GPIO
■ Operating temp. range
Oscillation-stoppage detection, frequency measurement, CRC, IWDT, self-
Ethernet MAC (1) (not in RX631 Group products)
Host/function or OTG controller (1) and function controller (1) with full-
CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up to 3
SCI with multiple functionalities (up to 13)
Choose from among asynchronous mode, clock-synchronous mode, smart-
RSPI for high-speed transfer (up to 3)
Buses for high-speed data transfer (max. operating frequency of 50 MHz)
8 CS areas (8 × 16 Mbytes)
Multiplexed address data or separate address lines are selectable per area.
8-, 16-, or 32-bit bus space is selectable per area
Independent SDRAM area (128 Mbytes)
16-bit MTU2: input capture, output compare, PWM waveform output,
16-bit TPU: input capture, output compare, phase-counting mode (12
8-bit TMR (4 channels)
16-bit compare-match timers (4 channels)
Up to 21 12-bit channels, and incorporating 1 sample-and-hold circuit
Addition of results of A/D conversion (in the 12-bit converter)
Self diagnosis (for the 10-bit converter)
5-V tolerance, open drain, input pull-up, switchable driving ability
–40°C to +85°C
the chip
important registers against overwriting.
diagnostic function for the A/D converter, etc.
speed USB 2.0 transfer
modules)
card interface mode, simplified SPI, simplified I2C, and extended serial
mode.
I
phase-counting mode (6 channels)
channels)
Up to 8 10-bit channels, and incorporating 1 sample-and-hold circuit
2
C bus interface for transfer at up to 1 Mbps (up to 4)
PLQP0176KB-A 24 × 24 mm, 0.5-mm pitch
PLQP0144KA-A 20 × 20mm, 0.5-mm pitch
PLQP0100KB-A 14 × 14mm, 0.5-mm pitch
PTLG0177KA-A 8 × 8 mm, 0.5-mm pitch
PTLG0145KA-A 7 × 7mm, 0.5-mm pitch
PTLG0100KA-A 5.5 × 5.5mm, 0.5-mm pitch
PLBG0176GA-A 13 × 13mm, 0.8-mm pitch
Preliminary
R01DS0098EJ0090
Page 1 of 106
Dec 27, 2011
Rev.0.90