R5F56308DDFP Renesas Electronics Corporation., R5F56308DDFP Datasheet

R5F56308DDFP

Manufacturer Part Number

R5F56308DDFP

Description

LQFP 100

Manufacturer

Renesas Electronics Corporation.

Datasheets

1.R5F5630ACDLK.pdf (107 pages)

2.R5F56308DDFP.pdf (165 pages)

Specifications of R5F56308DDFP

Pack_quantity

Comm_code

85423190

Lead_time

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

R5F56308DDFP#V0

Manufacturer:

Renesas Electronics America

Quantity:

10 000

Company:

Meier Automation Equipment Co., Limited

Part Number:

R5F56308DDFP#VO

Manufacturer:

RENESAS/瑞萨

Quantity:

20 000

Current page: 1 of 107
Download datasheet (766Kb)

RX630 Group

Renesas MCUs

100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS,

up to 2-MB flash memory, USB 2.0 full-speed function interface, CAN, 10- & 12-bit ADC,

RTC, up to 22 comms interfaces

R01DS0060EJ0050 Rev.0.50

May 13, 2011

Features

■ 32-bit RX CPU core

■ Low-power design and architecture

■ On-chip main flash memory, no wait states

■ On-chip data flash memory

■ On-chip SRAM, no wait states

■ DMA

■ Reset and supply management

■ Clock functions

■ Real-time clock

■ Independent watchdog timer

 Max. operating frequency: 100 MHz

 Single precision 32-bit IEEE-754 floating point

 Two types of multiply-and-accumulation unit (between memories

 32-bit multiplier (fastest instruction execution takes one CPU

 Divider (fastest instruction execution takes two CPU clock cycles)

 Fast interrupt

 CISC Harvard architecture with 5-stage pipeline

 Variable-length instructions: Ultra-compact code

 Supports the memory protection unit (MPU)

 Operation from a single 2.7- to 3.6-V supply

 Low power consumption: A product that supports all peripheral

 RTC is capable of operation from a dedicated power supply (min.

 Four low-power modes

 100-MHz operation, 10-ns read cycle (no wait states)

 384-Kbyte to 2-Mbyte capacities

 User code programmable via the USB, SCI, or JTAG

 Max. 32 Kbytes, reprogrammable up to 100,000 times

 Programming/erasing as background operations (BGOs)

 32- to 128-Kbyte capacities

 For instructions and operands

 Can provide backup on deep software standby

 DMAC: Incorporates four channels

 DTC

 Power-on reset (POR)

 Low voltage detection (LVD) with voltage settings

 External crystal oscillator or internal PLL for operation at 4 to 16

 Internal 125-kHz LOCO and 50-MHz HOCO

 Dedicated 125-kHz LOCO for the IWDT

 Frequency of the oscillator for sub-clock generation: 32 kHz

 Adjustment functions (30 seconds, leap year, and error)

 Time capture function

 125-kHz LOCO clock operation

Capable of 165 DMIPS in operation at 100 MHz

and between registers)

clock cycle)

JTAG and FINE (two-line) debugging interfaces

functions draws only 500 μA/MHz.

operating voltage: 2 V).

MHz

(for capturing times in response to event-signal input on external

pins)

Specifications in this document are tentative and subject to change.

■ Useful functions for IEC60730 compliance

■ Up to 22 communications interfaces

■ External address space

■ Up to 20 extended-function timers

■ A/D converter for 1-MHz Operation

■ 10-bit D/A converter: 2 channels

■ Temperature sensor for measuring temperature

■ Register write protection can protect values in

■ Up to 148 pins for GPIO

■ Operating temp. range

 Oscillation-stoppage detection, frequency measurement, CRC,

 USB 2.0 full-speed function interface (1)

 CAN (compliant with ISO11898-1), incorporating 32 mailboxes

 SCI with multiple functionalities (up to 13)

 I

 RSPI for high-speed transfer (up to 3)

 8 CS areas (8 × 16 Mbytes)

 Multiplexed address data or separate address lines are selectable

 8-, 16-, or 32-bit bus space is selectable per area

 16-bit MTU2: input capture, output capture, complementary PWM

 16-bit TPU: input capture, output capture, phase-counting mode

 8-bit TMR (4 channels)

 16-bit compare-match timers (4 channels)

 Up to 21 12-bit channels, and incorporating 1 sample-and-hold

 Up to 8 10-bit channels, and incorporating 1 sample-and-hold

 Addition of results of A/D conversion (in the 12-bit converter)

 Self diagnosis (for the 10-bit converter)

 5-V tolerance, open drain, input pull-up, switchable driving ability

 –40 C to +85C

within the chip

important registers against overwriting.

IWDT, self-diagnostic function for the AD converter

(up to 3)

Choose from among asynchronous mode, clock-synchronous

mode, smart-card interface mode, simplified SPI, simplified I2C,

and extended serial mode.

per area.

output, phase-counting mode (6 channels)

(12 channels)

circuit

Preliminary

C bus interface for transfer at up to 1 Mbps (up to 4)

PLQP0176KB-A 24×24mm, 0.5mm pitch

PLQP0144KA-A 20×20mm, 0.5mm pitch

PLQP0100KB-A 14×14mm, 0.5mm pitch

PLQP0080KB-A 12×12mm, 0.5mm pitch

DATASHEET

R01DS0060EJ0050

Page 1 of 107

May 13, 2011

Rev.0.50

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