74HCT393 Philips Semiconductors, 74HCT393 Datasheet

74HCT393

Manufacturer Part Number

74HCT393

Description

Manufacturer

Philips Semiconductors

Datasheets

1.74HCT393BQ.pdf (25 pages)

2.74HCT393.pdf (7 pages)

Specifications of 74HCT393

Case

SOP

Date_code

06+

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1. General description

2. Features

3. Quick reference data

The 74HC393; HCT393 is a high-speed Si-gate CMOS device and is pin compatible with

Low-power Schottky TTL (LSTTL). It is speciﬁed in compliance with JEDEC standard

no. 7A.

The 74HC393; 74HCT393 contains 4-bit binary ripple counters with separate clocks

(1CP and 2 CP) and master reset (1MR and 2MR) inputs to each counter.

The operation of each half of the 74HC393; 74HCT393 is the same as the 74HC93;

74HCT93, except no external clock connections are required.

The counters are triggered by a HIGH-to-LOW transition of the clock inputs.

The counter outputs are internally connected to provide clock inputs to succeeding

stages. The outputs of the ripple counter do not change synchronously and should not be

used for high-speed address decoding.

The master resets (1MR and 2MR) are active-HIGH asynchronous inputs to each 4-bit

counter. A HIGH level on the nMR input overrides the clock and sets the outputs LOW.

Table 1:

GND = 0 V; T

Symbol

74HC393

PHL

clk(max)

74HC393; 74HCT393

Dual 4-bit binary ripple counter

Rev. 03 — 6 September 2005

Two 4-bit binary counters with individual clocks

Divide by any binary module up to 28 in one package

Two master resets to clear each 4-bit counter individually

, t

PLH

Quick reference data

Parameter

propagation delay

maximum clock

frequency

input capacitance

power dissipation

capacitance (per gate)

amb

nCP to nQ0

nQx to nQ(x+1)

nMR to nQx

= 25 C; t

= t

= 6 ns.

Conditions

= 15 pF; V

= 5 V

[1] [2]

Product data sheet

Min

Typ

3.5

Max

Unit

MHz

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