MC14094B
8−Stage Shift/Store Register
with Three−State Outputs
for each stage and a 3−state output from each latch.
seventh stage to two serial outputs. The Q
high−speed cascaded systems. The Q
following negative clock transition for use in low−speed cascaded
systems.
transition of the strobe input. Data propagates through the latch while
strobe is high.
which are placed in the high−impedance state by a logic Low on
Output Enable.
Features
•
•
•
•
•
•
•
•
1. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
(e.g., either V
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2005
Symbol
V
I
The MC14094B combines an 8−stage shift register with a data latch
Data is shifted on the positive clock transition and is shifted from the
Data from each stage of the shift register is latched on the negative
Outputs of the eight data latches are controlled by 3−state buffers
in
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level
Schottky TTL Load Over the Rated Temperature Range
Negative Clock Transitions
in
3−State Outputs
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Input Diode Protection
Data Latch
Dual Outputs for Data Out on Both Positive and
Useful for Serial−to−Parallel Data Conversion
Pin−for−Pin Compatible with CD4094B
Pb−Free Packages are Available*
V
T
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
P
, V
, I
T
T
stg
DD
A
D
L
out
out
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation, per Package
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
SS
(DC or Transient)
(DC or Transient) per Pin
(Note 1)
(8−Second Soldering)
or V
v (V
DD
in
). Unused outputs must be left open.
Parameter
or V
(Voltages Referenced to V
out
) v V
DD
.
S
output data is shifted on the
in
and V
S
−0.5 to V
output data is for use in
SS
−0.5 to +18.0
−55 to +125
−65 to +150
out
)
Value
± 10
500
260
should be constrained
DD
+ 0.5
1
Unit
mW
mA
°C
°C
°C
V
V
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
A
WL, L
YY, Y
WW, W
G
CASE 751B
CASE 948F
SOEIAJ−16
TSSOP−16
DT SUFFIX
CASE 648
CASE 966
P SUFFIX
D SUFFIX
F SUFFIX
PDIP−16
SOIC−16
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
Publication Order Number:
16
1
16
16
1
1
DIAGRAMS
16
MARKING
MC14094BCP
AWLYYWWG
1
MC14094B
AWLYWW
MC14094B/D
14094BG
ALYWG
ALYW
094B
14