74ALVC16373DTR ON Semiconductor, 74ALVC16373DTR Datasheet

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74ALVC16373DTR

Manufacturer Part Number
74ALVC16373DTR
Description
IC LATCH TRANSPRNT 16BIT 48TSSOP
Manufacturer
ON Semiconductor
Series
74ALVCr
Datasheet

Specifications of 74ALVC16373DTR

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
1.65 V ~ 3.6 V
Independent Circuits
2
Delay Time - Propagation
1.1ns
Current - Output High, Low
24mA, 24mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
74ALVC16373DTROS
74ALVC16373
Low−Voltage 1.8/2.5/3.3 V
16−Bit Transparent Latch
With 3.6 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
16−bit transparent latch. It is designed for very high−speed, very
low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The
ALVC16373 is byte controlled, with each byte functioning identically,
but independently. Each byte has separate Output Enable and Latch
Enable inputs. These control pins can be tied together for full 16−bit
operation.
3.6 V−tolerant outputs. When the Latch Enable (LEn) inputs are
HIGH, data on the Dn inputs enters the latches. In this condition, the
latches are transparent, (a latch output will change state each time its D
input changes). When LE is LOW, the latch stores the information that
was present on the D inputs a setup time preceding the
HIGH−to−LOW transition of LE. The 3−state outputs are controlled
by the Output Enable (OEn) inputs. When OE is LOW, the outputs are
enabled. When OE is HIGH, the standard outputs are in the high
impedance state, but this does not interfere with new data entering into
the latches.
†To ensure the outputs activate in the 3−state condition, the output enable pins
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 1
should be connected to V
determined by the current sinking capability of the output connected to the OE pin.
The 74ALVC16373 is an advanced performance, non−inverting
The 74ALVC16373 contains 16 D−type latches with 3−state
Substantially Reduces System Power Requirements
>200 V
Designed for Low Voltage Operation: V
3.6V Tolerant Inputs and Outputs
High Speed Operation: 3.6 ns max for 3.0 to 3.6 V
Static Drive: ±24 mA Drive at 3.0 V
Supports Live Insertion and Withdrawal
I
Near Zero Static Supply Current in All Three Logic States (40 mA)
Latchup Performance Exceeds ±250 mA @ 125°C
ESD Performance: Human Body Model >2000 V; Machine Model
Second Source to Industry Standard 74ALVC16373
OFF
Specification Guarantees High Impedance When V
±12 mA Drive at 2.3 V
±4 mA Drive at 1.65 V
CC
through a pull−up resistor. The value of the resistor is
4.5 ns max for 2.3 to 2.7 V
6.8 ns max for 1.65 to 1.95 V
CC
= 1.65−3.6 V
CC
1
= 0 V
48
PIN NAMES
74ALVC16373DTR
Pins
OEn
LEn
D0−D15
O0−O15
CASE 1201
DT SUFFIX
TSSOP−48
Device
1
ORDERING INFORMATION
A
Location
WL
YY
WW
http://onsemi.com
Function
Output Enable Inputs
Latch Enable Inputs
Inputs
Outputs
Package
TSSOP
= Assembly
= Wafer Lot
= Year
= Work Week
48
1
Publication Order Number:
MARKING DIAGRAM
74ALVC16373DT
AWLYYWW
2500/Tape & Reel
74ALVC16373/D
Shipping

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74ALVC16373DTR Summary of contents

Page 1

... OE pin. © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev 1.65−3 PIN NAMES Pins OEn LEn D0−D15 O0−O15 † 74ALVC16373DTR 1 http://onsemi.com MARKING DIAGRAM 48 74ALVC16373DT 1 AWLYYWW TSSOP−48 DT SUFFIX CASE 1201 Assembly Location ...

Page 2

OE1 LE1 GND GND ...

Page 3

MAXIMUM RATINGS (Note 1) Symbol V DC Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Sink/Source Current ...

Page 4

DC ELECTRICAL CHARACTERISTICS Symbol Characteristic V HIGH Level Input Voltage (Note LOW Level Input Voltage (Note HIGH Level Output Voltage OH V LOW Level Output Voltage OL I Input Leakage Current I I 3−State ...

Page 5

AC CHARACTERISTICS (Note 10 Symbol Parameter t Propagation Delay PLH PHL t Propagation Delay PLH PHL t Output Enable Time to PZH t High and Low Level PZL t Output ...

Page 6

OEn t t PZH PHZ PZL PLZ On Vm WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES 2.0ns, 10 1MHz Symbol V ...

Page 7

PULSE GENERATOR R T TEST PLH PHL PZL PLZ PZH PHZ equivalent (Includes jig and probe capacitance 500 W or equivalent L R ...

Page 8

SEE NOTE 2 FOR MACHINE REFERENCE ONLY INCLUDING DRAFT AND RADII CONCENTRIC AROUND B R MIN. TAPE AND COMPONENTS SHALL PASS AROUND RADIUS R" WITHOUT DAMAGE BENDING RADIUS MAXIMUM COMPONENT ROTATION 10° TYPICAL COMPONENT CAVITY ...

Page 9

MIN (0.06") 20.2 mm MIN A (0.795") FULL RADIUS Figure 8. Reel Dimensions REEL DIMENSIONS Tape Size A Max 24 mm 360 mm 24 2.0 mm, −0.0 (14.173") (0.961" + 0.078", −0.00) DIRECTION OF FEED BARCODE ...

Page 10

TAPE TRAILER (Connected to Reel Hub) NO COMPONENTS CAVITY TOP TAPE 160 mm MIN TAPE K É É É É É É É É É É É É É É L É É É É É É É É É ...

Page 11

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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