74ALVCH16373TTR STMicroelectronics, 74ALVCH16373TTR Datasheet

IC TXRX 16BIT LV 3ST 48-TSSOP

74ALVCH16373TTR

Manufacturer Part Number
74ALVCH16373TTR
Description
IC TXRX 16BIT LV 3ST 48-TSSOP
Manufacturer
STMicroelectronics
Series
74ALVCHr
Datasheet

Specifications of 74ALVCH16373TTR

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
1.65 V ~ 3.6 V
Independent Circuits
2
Delay Time - Propagation
1ns
Current - Output High, Low
24mA, 24mA
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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74ALVCH16373TTR
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DESCRIPTION
The 74ALVCH16373 is a low voltage CMOS 16
BIT D-TYPE LATCH with 3 STATE OUTPUTS
NON
silicon gate and five-layer metal wiring C
technology. It is ideal for low power and very high
speed 1.65 to 3.6V applications; it can be
interfaced to 3.6V signal environment for both
inputs and outputs.
These 16 bit D-TYPE latches are bite controlled
by two latch enable inputs (nLE) and two output
enable inputs (OE).
While the nLE input is held at a high level, the nQ
outputs will follow the data input precisely.
When the nLE is taken low, the nQ outputs will be
in a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.This device is designed to be
used with 3 state memory address drivers, etc.
Active bus-hold circuitry holds unused or undriven
inputs at a valid logic state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 2003
PIN AND FUNCTION COMPATIBLE WITH
3.6V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED :
t
t
t
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
|I
|I
OPERATING VOLTAGE RANGE:
V
BUS HOLD PROVIDED ON DATA INPUTS
74 SERIES 16373
LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
PD
PD
PD
OH
OH
OH
CC
= 3.6 ns (MAX.) at V
= 4.5 ns (MAX.) at V
=
| = I
| = I
| = I
LOW VOLTAGE CMOS 16-BITD-TYPE LATCH (3-STATE)
(OPR) = 1.65V to 3.6V
INVERTING fabricated with sub-micron
6.5 ns (MAX.) at V
OL
OL
OL
= 24mA (MIN) at V
= 18mA (MIN) at V
= 4mA (MIN) at V
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
CC
CC
CC
= 3.0 to 3.6V
= 2.3 to 2.7V
CC
= 1.65V
CC
CC
= 1.65V
= 3.0V
= 2.3V
2
MOS
ORDER CODES
PIN CONNECTION
PACKAGE
TSSOP
74ALVCH16373
TUBE
TSSOP
74ALVCH16373TTR
T & R
1/11

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74ALVCH16373TTR Summary of contents

Page 1

... All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. February 2003 = 3.0 to 3.6V = 2.3 to 2.7V = 1.65V = 3. 2.3V ORDER CODES CC = 1.65V CC PACKAGE TSSOP PIN CONNECTION 2 MOS 74ALVCH16373 TSSOP TUBE T & R 74ALVCH16373TTR 1/11 ...

Page 2

INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1 1OE 3 State Output Enable Input (Active LOW 1Q0 to 1Q7 3-State Outputs 11, 12 13, 14, 16, 17, ...

Page 3

LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Output Voltage (OFF State Output Voltage (High or Low State) (note Input Diode Current IK I ...

Page 4

DC SPECIFICATIONS Symbol Parameter V High Level Input 1.65 to 1.95 IH Voltage V Low Level Input 1.65 to 1.95 IL Voltage V High Level Output OH Voltage V Low Level Output OL Voltage I Input Leakage I Current ...

Page 5

AC ELECTRICAL CHARACTERISTICS Symbol Parameter t t Propagation Delay 1.65 to 1.95 PLH PHL Time Propagation Delay 1.65 to 1.95 PLH PHL Time Output Enable Time 1.65 to 1.95 PZL ...

Page 6

CAPACITIVE CHARACTERISTICS Symbol Parameter C Input Capacitance Control IN Inputs C Input Capacitance Data Inputs IN C Output Capacitance OUT C Power Dissipation Capacitance PD Output enabled (note 1) C Power Dissipation Capacitance PD Output disabled (note 1) 1) ...

Page 7

WAVEFORM PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 74ALVCH16373 7/11 ...

Page 8

WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 8/11 ...

Page 9

TSSOP48 MECHANICAL DATA mm. DIM. MIN 0. 0.17 c 0.09 D 12.4 E 8.1 BSC E1 6.0 e 0.5 BSC K 0˚ PIN 1 IDENTIFICATION 1 TYP MAX. MIN. 1.2 ...

Page 10

Tape & Reel TSSOP48 MECHANICAL DATA DIM. MIN 12 8.7 Bo 13.1 Ko 1.5 Po 3.9 P 11.9 10/11 mm. TYP MAX. MIN. 330 13.2 0.504 0.795 2.362 30.4 8.9 0.343 ...

Page 11

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...

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