CY7C150-35DMB Cypress Semiconductor Corporation., CY7C150-35DMB Datasheet

CY7C150-35DMB

Manufacturer Part Number

CY7C150-35DMB

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C150-15DMB.pdf (11 pages)

2.CY7C150-35DMB.pdf (11 pages)

3.CY7C150-25DMB.pdf (8 pages)

Specifications of CY7C150-35DMB

Date_code

00+

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Download datasheet (324Kb)

Cypress Semiconductor Corporation

Document #: 38-05024 Rev. *A

Features

Functional Description

The CY7C150 is a high-performance CMOS static RAM de-

signed for use in cache memory, high-speed graphics, and

data-acquisition applications. The CY7C150 has a memory re-

set feature that allows the entire memory to be reset in two

memory cycles.

Selection Guide

• Memory reset function

• 1024 x 4 static RAM for control store in high-speed com-

• CMOS for optimum speed/power

• High speed

• Low power

• Separate inputs and outputs

• 5-volt power supply 10% tolerance in both commercial

• Capable of withstanding greater than 2001V static dis-

• TTL-compatible inputs and outputs

Maximum Access Time (ns)

Maximum Operating Current (mA)

Logic Block Diagram

puters

and military

charge

— 10 ns (commercial)

— 12 ns (military)

— 495 mW (commercial)

— 550 mW (military)

COLUMN DECODER

DATAINPUT

CONTROL

DECODER

COLUMN

64 x 64

ARRA Y

Commercial

Military

Commercial

Military

•

3901 North First Street

C150–1

7C150 10

Separate I/O paths eliminates the need to multiplex data in

and data out, providing for simpler board layout and faster sys-

tem performance. Outputs are three-stated during write, reset,

deselect, or when output enable (OE) is held HIGH, allowing

for easy memory expansion.

Reset is initiated by selecting the device (CS = LOW) and tak-

ing the reset (RS) input LOW. Within two memory cycles all

bits are internally cleared to zero. Since chip select must be

LOW for the device to be reset, a global reset signal can be

employed, with only selected devices being cleared at any giv-

en time.

Writing to the device is accomplished when the chip select

(CS) and write enable (WE) inputs are both LOW. Data on the

four data inputs (D

specified on the address pins (A

Reading the device is accomplished by taking chip select (CS)

and output enable (OE) LOW while write enable (WE) remains

HIGH. Under these conditions, the contents of the memory

location specified on the address pins will appear on the four

output pins (O

The output pins remain in high-impedance state when chip

enable (CE) or output enable (OE) is HIGH, or write enable

(WE) or reset (RS) is LOW.

A die coat is used to insure alpha immunity.

•

7C150 12

San Jose

100

GND

O 0

O 1

Pin Configuration

D 0

D 1

A 3

A 4

A 5

A 6

A 7

A 8

A 9

through O

7C150 15

DIP/SOIC

Top View

7C150

) is written into the memory location

•

100

1Kx4 Static RAM

CA 95134

C150-2

through A

Revised January 18, 2003

V CC

A 2

A 1

A 0

D 3

D 2

O 3

O 2

7C150 25

100

•

CY7C150

408-943-2600

7C150 35

100

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