MC100EP52D ON Semiconductor, MC100EP52D Datasheet

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MC100EP52D

Manufacturer Part Number
MC100EP52D
Description
Manufacturer
ON Semiconductor
Datasheets

Specifications of MC100EP52D

Case
SOP8
Date_code
07

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MC10EP52, MC100EP52
3.3V / 5V ECL Differential
Data and Clock D Flip-Flop
Description
flip−flop. The device is pin and functionally equivalent to the EL52
device.
LOW and is transferred to the slave, and thus the outputs, upon a
positive transition of the clock. The differential clock inputs of the
EP52 allow the device to also be used as a negative edge triggered
device.
conditions (pulled down to V
stable.
Features
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 7
The MC10EP/100EP52 is a differential data, differential clock D
Data enters the master portion of the flip−flop when the clock is
The EP52 employs input clamping circuitry so that under open input
The 100 Series contains temperature compensation.
330 ps Typical Propagation Delay
Maximum Frequency u 4 GHz Typical
PECL Mode: V
NECL Mode: V
Open Input Default State
Safety Clamp on Inputs
Q Output Will Default LOW with Inputs Open or at V
Pb−Free Packages are Available
CC
CC
= 3.0 V to 5.5 V with V
= 0 V with V
EE
) the outputs of the device will remain
EE
= −3.0 V to −5.5 V
EE
= 0 V
EE
1
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
CASE 506AA
CASE 948R
MN SUFFIX
DT SUFFIX
CASE 751
D SUFFIX
TSSOP−8
8
*For additional marking information, refer to
SOIC−8
8
H
K
5T
3O
(Note: Microdot may be in either location)
DFN8
Application Note AND8002/D.
1
1
ORDERING INFORMATION
= MC10
= MC100 L
= MC10
= MC100 W = Work Week
http://onsemi.com
A
Y
M = Date Code
G
8
1
8
1
Publication Order Number:
= Assembly Location
= Wafer Lot
= Year
= Pb−Free Package
HEP52
ALYWG
ALYW
1
HP52
G
G
DIAGRAMS*
MARKING
4
8
1
MC10EP52/D
8
1
KEP52
ALYW
ALYWG
KP52
1
G
G
4

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