PI74ALVCH16260A Pericom Semiconductor, PI74ALVCH16260A Datasheet

PI74ALVCH16260A

Manufacturer Part Number

PI74ALVCH16260A

Description

IC 12/14-BIT MUX/LATCH 56-TSSOP

Manufacturer

Pericom Semiconductor

Series

74ALVCHr

Datasheet

1.PI74ALVCH16260A.pdf (6 pages)

Specifications of PI74ALVCH16260A

Logic Type

D-Type, Addressable

Circuit

12:24

Output Type

Tri-State

Voltage - Supply

2.3 V ~ 3.6 V

Independent Circuits

Delay Time - Propagation

1ns

Current - Output High, Low

24mA, 24mA

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

56-TSSOP

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

PI74ALVCH16260A

Manufacturer:

Quantity:

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1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2

Product Features

• PI74ALVCH16260 is designed for low voltage operation

• V

• Hysteresis on all inputs

• Typical V

• Bus Hold retains last active bus state during 3-State,

• Industrial operation at –40°C to +85°C

• Packages available:

Logic Block Diagram

eliminating the need for external pullup resistors

– 56-pin 240 mil wide plastic TSSOP (A)

< 0.8V at V

< 2.0V at V

= 2.3V to 3.6V

06-0132

OHV

OLP

(Output Ground Bounce)

(Output V

LEA1B

LEA2B

OE2B

OE1B

= 3.3V, T

LE1B

LE2B

OEA

SEL

= 25°C

Undershoot)

TO 11 OTHER CHANNELS

12-Bit To 24-Bit Multiplexed D-Type Latch

Product Description

The PI74ALVCH16260 is a 12-bit to 24-bit multiplexed D-type latch

designed for 2.3V to 3.6 V

where two separate datapaths must be multiplexed onto, or

demultiplexed from, a single data path.

Typical applications include multiplexing and/or demultiplexing

address and data information in microprocessor or bus-interface

and in memory-interleaving.

Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available

for address and/or data transfer. The output-enable (OE1B, OE2B,

and OEA) inputs control bus transceiver functions. The OE1B and

OE2B control signals also allow bank control in the A-to-B direction.

Address and/or data information can be stored using the internal

storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B)

inputs are used to control data storage. When the latch-enable input

is HIGH, the latch is transparent. When the latch-enable input goes

LOW, the data present at the inputs is latched and remains latched

until the latch-enable input is returned HIGH.

To ensure high-impedance state during power up or power down,

OE should be tied to V

value is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating

data inputs at a valid logic level.

through a pullup resistor whose minimum

operation. It is used in applications

PI74ALVCH16260

with 3-State Outputs

2B1

1B1

PS8089D

05/24/06

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PI74ALVCH16260A Summary of contents

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... Packaging Mechanical Ordering Information Ordering Code PI74ALVCH16260A Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • Adding an X suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 06-0132 Package Code A 56-pin 240 mil wide plastic TSSOP (A) 6 PI74ALVCH16260 ...

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