74LVQ573SJX Fairchild Semiconductor, 74LVQ573SJX Datasheet
74LVQ573SJX
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74LVQ573SJX Summary of contents
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... OE 3-STATE Output Enable Input O –O 3-STATE Latch Outputs 0 7 © 2001 Fairchild Semiconductor Corporation Features Ideal for low power/low noise 3.3V applications Implements patented EMI reduction circuitry Available in SOIC JEDEC, SOIC EIAJ, and QSOP packages Guaranteed simultaneous switching noise level and dynamic threshold performance ...
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Functional Description The LVQ573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the D inputs enters the latches. In this condition n the latches are transparent, i.e., a latch output ...
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Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Input Voltage ( Output Diode Current ( ...
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AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL PLH Propagation Delay PLH PHL n t Output Enable Time PZL t PZH t Output Disable Time PHZ t PLZ ...
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Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 6 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...