74LVX373M Fairchild Semiconductor, 74LVX373M Datasheet - Page 2
74LVX373M
Manufacturer Part Number
74LVX373M
Description
IC LATCH TRANSPARENT OCT 20-SOIC
Manufacturer
Fairchild Semiconductor
Series
74LVXr
Datasheet
1.74LVX373MTC.pdf
(7 pages)
Specifications of 74LVX373M
Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2 V ~ 3.6 V
Independent Circuits
1
Delay Time - Propagation
6ns
Current - Output High, Low
4mA, 4mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Number Of Circuits
8
Logic Family
74LV
Polarity
Non-Inverting
High Level Output Current
- 4 mA
Propagation Delay Time
18.5 ns at 2.7 V, 13.2 ns at 3.3 V
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Functional Description
The LVX373 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the D
dition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
n
inputs enters the latches. In this con-
2
sition of LE. The 3-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW, the
standard outputs are in the 2-state mode. When OE is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the latches.