PACVGA100Q California Micro Devices Corporation, PACVGA100Q Datasheet

PACVGA100Q

Manufacturer Part Number

PACVGA100Q

Description

Manufacturer

California Micro Devices Corporation

Datasheet

1.PACVGA100Q.pdf (5 pages)

Specifications of PACVGA100Q

Case

SSOP16

Date_code

99+

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02/14/02

Features

•

Applications

•

Typical Application Circuit

R1, R2 required

only for VGA101

Note 1: For best ESD protection, minimize R/G/B trace lengths

Seven channel ESD protection

side (HBM)

per channel, connector side (IEC 61000-4-2 Level

4 standard)

Low loading capacitance—4.5pF typical

16-pin QSOP package

ESD protection and termination resistors for VGA

(video) port interfaces

Desktop PCs

Notebook computers

LCD monitors

15 kV ESD protection per channel, connector

8 kV contact, 15 kV air discharge ESD protection

DDC_Data

DDC_Clk

215 Topaz Street, Milpitas, California 95035

H-Sync

V-Sync

between the PACVGA100/101 device and the video

connector.

Blue

Red

Grn

R1 R2

VGA Port ESD Protection and Termination Network

(See Note 1)

BYPASS

0.2uF

L Tel: (408) 263-3214

H-Sync

V-Sync

DDC_Data

DDC_Clk

Simplified Electrical Schematic

Product Description

The PACVGA100/101 functions as a transmission line

termination and ESD protection device for video appli-

cations. It provides 75 ohm parallel terminations for

video R, G, and B lines and series terminations for the

Horizontal Sync, Vertical Sync and the two DDC lines

which serve as Plug and Play logic signals. In addition,

all interface lines provide Level 4 ESD protection per

the IEC 61000-4-2 contact discharge specification. The

PACVGA100 provides internal pull-up resistors (R3) for

the two DDC lines whereas the PACVGA101 omits

these internal pull-ups so that different pull-up resistor

values can be added externally.

L Fax: (408) 263-7846 L www.calmicro.com

* R3 omitted for PACVGA101

R3 = 2.2KΩ (for PACVGA100 only)

R1 = 75Ω, R2 = 33Ω

PACVGA100/101

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