74LVX573MTC Fairchild Semiconductor, 74LVX573MTC Datasheet - Page 2
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74LVX573MTC
Manufacturer Part Number
74LVX573MTC
Description
IC LATCH OCTAL LV 3STATE 20TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LVXr
Datasheet
1.74LVX573MTCX.pdf
(7 pages)
Specifications of 74LVX573MTC
Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2 V ~ 3.6 V
Independent Circuits
1
Delay Time - Propagation
5.9ns
Current - Output High, Low
4mA, 4mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Number Of Circuits
8
Logic Family
74LV
Polarity
Non-Inverting
Input Bias Current (max)
4 uA
High Level Output Current
- 4 mA
Low Level Output Current
4 mA
Propagation Delay Time
18 ns at 2.7 V, 12.8 ns at 3.3 V
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LVX573MTCX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
www.fairchildsemi.com
Functional Description
The LVX573 contains eight D-type latches. When the
enable (LE) input is HIGH, data on the D
latches. In this condition the latches are transparent, i.e., a
latch output will change state each time its D input
changes. When LE is LOW the latches store the informa-
tion that was present on the D inputs a setup time preced-
ing the HIGH-to-LOW transition of LE. The 3-STATE
buffers are controlled by the Output Enable (OE) input.
When OE is LOW, the buffers are enabled. When OE is
HIGH the buffers are in the high impedance mode but this
does not interfere with entering new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
n
inputs enters the
2
Truth Table
H
L
Z
X
O
0
LOW Voltage
High Impedance
HIGH Voltage
Immaterial
Previous O
OE
H
L
L
L
0
before HIGH-to-LOW transition of Latch Enable
Inputs
LE
H
H
L
X
D
H
X
X
L
Outputs
O
O
H
Z
L
n
0