74AHC259D,112 NXP Semiconductors, 74AHC259D,112 Datasheet
74AHC259D,112
Specifications of 74AHC259D,112
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74AHC259D,112 Summary of contents
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Rev. 02 — 15 May 2008 1. General description The 74AHC259; 74AHCT259 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL specified in compliance with JEDEC standard ...
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... NXP Semiconductors I Input levels: N For 74AHC259: CMOS level N For 74AHCT259: TTL level I ESD protection: N HBM EIA/JESD22-A114E exceeds 2000 EIA/JESD22-A115-A exceeds 200 V N CDM EIA/JESD22-C101C exceeds 1000 V I Multiple package options I Specified from +85 C and from +125 C 3. Ordering information Table 1. ...
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... NXP Semiconductors Fig 3. Functional diagram 5. Pinning information 5.1 Pinning Fig 4. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin GND 74AHC_AHCT259_2 Product data sheet 74AHC259; 74AHCT259 1-of-8 DECODER LATCHES 74AHC259 74AHCT259 GND 8 001aai126 Description address input address input address input ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin Functional description [1] Table 3. Function table Operating mode Input MR Reset (clear) L Demultiplexer L (active HIGH 8-channel) decoder (when Memory (no action) H Addressable latch H [ HIGH voltage level LOW voltage level don’t care HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition; ...
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... NXP Semiconductors Table 4. Operating mode select table [ HIGH voltage level LOW voltage level. 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I I input clamping current ...
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... NXP Semiconductors 9. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74AHC259 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage 4.0 mA 8.0 mA LOW-level output voltage 4.0 mA 8.0 mA input leakage GND ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions I input leakage GND current 5 supply current 5 additional per input pin supply current other pins input capacitance C output O capacitance 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V) ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t propagation MR to Qn; see pd delay pulse width LE HIGH or LOW; W see Figure LOW; see set-up time LE; see su and Figure ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t set-up time LE; see su and Figure 10 t hold time LE; see h and Figure 10 C power MHz dissipation capacitance [1] Typical values are measured at nominal supply voltage (V ...
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... NXP Semiconductors Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 6. Address input to output propagation delays D input LE input Qn output Measurement points are given in V and V are typical voltage output levels that occur with the output load. ...
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... NXP Semiconductors LE input D input Qn output Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. V and V are typical voltage output levels that occur with the output load Fig 9. Data input to latch enable input set-up and hold times ...
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... NXP Semiconductors Test data is given in Table Definitions test circuit termination resistance should be equal to output impedance load capacitance including jig and probe capacitance. L Fig 11. Load circuitry for measuring switching times Table 10. Test data Type Input V I 74AHC259 V CC 74AHCT259 3.0 V 74AHC_AHCT259_2 Product data sheet ...
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... NXP Semiconductors 12. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... Document ID Release date 74AHC_AHCT259_2 20080515 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table 74AHC_AHCT259_1 20000314 74AHC_AHCT259_2 Product data sheet 74AHC259 ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 14 Revision history ...