MC100EP101MNG ON Semiconductor, MC100EP101MNG Datasheet - Page 2

• Manufacturer Part Number: MC100EP101MNG
• Description: IC GATE OR/NOR QUAD 4INP 32-QFN
• Manufacturer: ON Semiconductor
• Series: 100EPr

Specifications of MC100EP101MNG

• Logic Type: NOR/OR Gate
• Number Of Circuits: 4
• Number Of Inputs: 16 Input (4, 4, 4, 4)
• Schmitt Trigger Input: No
• Output Type: Differential
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -

D0b
D0a
V
V
D0c
V
Q0
Q0
CC
CC
EE
Warning: All V
Power Supply to guarantee proper operation.
Figure 1. 32−Lead LQFP Pinout (Top View)
Table 2. TRUTH TABLE
* Pins will default LOW when left open.
25
26
27
28
29
30
31
32
Table 1. PIN DESCRIPTION
D0a*−D3d*
Q0−Q3, Q0−Q3
V
V
NC
EP for QFN−32,
only
PIN
Dna
L
H
X
X
X
H
D0d D1a
V
CC
EE
24
1
CC
CC
Q1
23
2
and V
Dnb
L
X
H
X
X
H
D1b
Q1
22
3
MC100EP101
EE
MC10EP101
D1c
pins must be externally connected to
Q2
21
4
Dnc
L
X
X
H
X
H
FUNCTION
ECL Data Inputs
ECL Data Outputs
Positive Supply
Negative Supply
No Connect
The Exposed Pad (EP) on the
QFN−32 package bottom is
thermally connected to the die
for improved heat transfer out
of package. The exposed pad
must be attached to a heat−
sinking conduit. The pad is
electrically connected to V
D1d
Q2
20
5
Dnd
L
X
X
X
H
H
D2a
Q3
19
6
D2b
Q3
18
7
Qn
L
H
H
H
H
H
V
D2c
17
8
CC
http://onsemi.com
16
15
14
13
12
10
11
9
Qn
H
L
L
L
L
L
EE
.
2
D2d
D3a
D3b
V
D3c
D3d
V
NC
CC
EE
V
V
Q1
Q1
Q2
Q2
Q3
Q3
CC
CC
Figure 2. 32−Lead QFN Pinout (Top View)
1
2
3
4
5
6
7
8
V
NC
32
CC
9
V
V
D
D
V
D
D
D
D
D
D
D
D
D
D
D
D
D
D
10
31
CC
EE
0c
1c
EE
3c
0a
0b
0d
1a
1b
1d
2a
2b
2d
3a
3b
3d
2c
Figure 3. Logic Diagram
D3d D3c V
Q0
30
11
MC100EP101
MC10EP101
Q0 V
12
29
28
13
EE
CC
D0a D0b D0c
D3b D3a D2d
14
27
15
26
16
25
Q
Q
Q
Q
Q
Q
Q
Q
2
0
0
1
1
2
3
3
24
23
22
21
20
19
18
17
D0d
D1a
D1b
D1c
D1d
D2a
D2b
D2c