ZL30160GGG Zarlink Semiconductor, ZL30160GGG Datasheet

ZL30160GGG

Manufacturer Part Number

ZL30160GGG

Description

Manufacturer

Zarlink Semiconductor

Datasheet

1.ZL30160.pdf (4 pages)

Specifications of ZL30160GGG

Lead_time

2 weeks

Current page: 1 of 4
Download datasheet (87Kb)

Features

•

Four independent clock channels

Programmable synthesizers generate any clock-

rate from 1 kHz to 720 MHz

Two precision synthesizers generate clocks with

jitter below 0.7 ps RMS for 10 G PHYs

Two general purpose synthesizers generate a wide

range of digital bus clocks

Programmable digital PLLs synchronize to any

clock rate from 1 kHz to 720 MHz

Flexible two-stage architecture translates between

arbitrary data rates, line coding rates and FEC

rates

Digital PLLs filter jitter from 14 Hz, 28 Hz, 56 Hz,

112 Hz, 224 Hz, 448 Hz or 896 Hz

Automatic hitless reference switching and digital

holdover on reference fail

Four reference inputs configurable as single ended

or differential

Eight LVPECL outputs and four LVCMOS outputs

JTAG

Ref2

Ref3

Osco

Ref0

Ref1

Osci

ZL30160

Single Ended

Master Clock

Differential /

JTAG

Reference Monitors

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

pwr_b

State Machine

Fr= Br

DPLL0

DPLL1

DPLL2

DPLL3

*Kr

Figure 1 - Functional Block Diagram

*Mr

GPIO

/Nr

Configuration

and Status

Zarlink Semiconductor Inc.

SPI / I

Four

Clock Generator 1 (Precision)

Clock Generator 3 (General Purpose)

Clock Generator 0 (Precision)

Clock Generator 2 (General Purpose)

Fs= Bs

•

Applications

•

Fs= Bs

Channel Universal Clock Translator

Synthesizer 1

Synthesizer 3

Synthesizer 0

Synthesizer 2

Eight outputs configurable as LVCMOS or

LVDS/LVPECL/HCSL

Operates from a single crystal resonator or clock

oscillator

Configurable via SPI/I2C interface

10 Gigabit linecards

Synchronous Ethernet, 10GBASE-R and

10 GBASE-W

OTN multiplexers and transponders

SONET/SDH, Fibre Channel, XAUI

*Ks

ZL30160GGG

ZL30160GGG2

*Ks

*16*Ms

*8*Ms

/Ns

*Pb Free Tin/Silver/Copper

Ordering Information

Div A

Div B

Div C

Div D

Div A

Div B

Div C

Div D

Div A

Div B

Div C

Div D

Div A

Div B

Div C

Div D

-40

100 Pin CABGA

100 Pin CABGA*

C to +85

Single Ended

Short Form Data Sheet

Differential /

Single Ended

LVCMOS

Outputs

LVPECL

Differential /

Outputs

LVCMOS

Outputs

LVPECL

Outputs

ZL30160

hpdiff0_p/n

hpdiff1_p/n

hpdiff2_p/n

hpdiff3_p/n

hpdiff4_p/n

hpdiff5_p/n

hpdiff6_p/n

hpdiff7_p/n

hpoutclk0

hpoutclk1

hpoutclk2

hpoutclk3

outclk0

outclk1

outclk2

outclk3

outclk4

outclk5

outclk6

outclk7

Trays

April 2010

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