SY100EP196VTITR Micrel Semiconductor, SY100EP196VTITR Datasheet

SY100EP196VTITR

Manufacturer Part Number

SY100EP196VTITR

Description

Manufacturer

Micrel Semiconductor

Datasheets

1.SY100EP196V.pdf (18 pages)

2.SY100EP196VTITR.pdf (18 pages)

Specifications of SY100EP196VTITR

Lead_time

2 weeks

Current page: 1 of 18
Download datasheet (633Kb)

■ Clock de-skewing

■ Timing adjustment

■ Aperture centering

M9999-072706

hbwhelp@micrel.com or (408) 955-1690

Micrel, Inc.

■ Pin-for-pin, plug-in compatible to the ON

■ Maximum frequency > 2.5GHz

■ Programmable range: 2.2ns to 12.2ns

■ 10ps increments

■ 30ps fine tuning range

■ PECL mode operating range: V

■ NECL mode operating range: V

■ Open input default state

■ Safety clamp on inputs

■ A logic high on the /EN pin will force Q to logic low

■ D[0:10] can accept either ECL, CMOS, or TTL inputs

■ V

■ Available in a 32-pin TQFP package

ECL Pro is a registered trademark of Micrel, Inc.

FEATURES

APPLICATIONS

TYPICAL APPLICATIONS CIRCUIT

Semiconductor MC100EP196

with V

of Unknown Phase

Fine Tune Voltage

output reference voltage

Data Signal

CLOCK+

CLOCK–

= 0V

= –3.0V to –5.5V

SY100EP196V

FTUNE

/IN

CONTROL

LOGIC

D[9:0]

= 3.0V to 5.5V

= 0V

Flip-Flop

3.3V/5V 2.5GHz PROGRAMMABLE

DELAY WITH FINE TUNE CONTROL

Q+

Q–

the time a logic signal takes to traverse from IN to Q. This

delay can vary from about 2.2ns to about 12.2ns. The input

can be PECL, LVPECL, NECL, or LVNECL.

word presented to SY100EP196V. The 10-bit width of this

latched control register allows for delay increments of

approximately 10ps. In addition, delay may be varied

continuously in about a 30ps range by setting the voltage at

the FTUNE pin.

SY100EP196V devices, for a wider delay range. Each

additional SY100EP196V effectively doubles the delay range

available.

accepts CMOS or TTL level signals, as well as the input

level at the IN± pins.

site at: www.micrel.com.

DESCRIPTION

TYPICAL PERFORMANCE

The SY100EP196V is a programmable delay line, varying

The delay varies in discrete steps based on a control

An eleventh control bit allows the cascading of multiple

For maximum flexibility, the control register interface

All support documentation can be found on Micrel’s web

CROSS REFERENCE TABLE

Micrel Semiconductor

SY100EP196VTI

SY100EP196VTITR

12000

10000

8000

6000

4000

2000

200 400 600 800 1000 1200

TAP (DIGITAL WORD)

Delay vs. Tap

ON Semiconductor

MC100EP196FA

MC100EP196FAR2

SY100EP196V

Rev.: E

Issue Date: July 2006

ECL Pro®

SY100EP196V

ECL Pro

Amendment: /0

ECL Pro®

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