PEX8518AC25BIG PLX Technology, Inc., PEX8518AC25BIG Datasheet

PEX8518AC25BIG

Manufacturer Part Number

PEX8518AC25BIG

Description

BGA

Manufacturer

PLX Technology, Inc.

Datasheet

1.PEX_8518-AC25BI_G.pdf (4 pages)

Specifications of PEX8518AC25BIG

Date_code

08+

Current page: 1 of 4
Download datasheet (471Kb)

Features

PEX 8518 General Features

o 16-lane PCI Express switch

o Up to five configurable ports

o 23mm x 23mm, 376-ball PBGA

o Typical Power: 2.6 Watts

PEX 8518 Key Features

o Standards Compliant

o High Performance

o Non-Transparent Bridging

o Flexible Configuration

o PCI Express Power Management

o Spread Spectrum Clock

o Quality of Service (QoS)

o Reliability, Availability, Serviceability

- Integrated SerDes

package

- PCI Express Base Specification, r1.1

- Standard SHPC Specification, r1.1

- Non-blocking internal architecture

- Full line rate on all ports

- Cut-Thru latency: 150ns

- Configurable Non-Transparent port

- Five highly flexible & configurable

- Configurable with strapping pins,

- Lane and polarity reversal

- Link power management states: L0,

- Device states: D0 and D3hot

- Vaux, WAKE#, Beacon support

- Dual clock domain

- Two Virtual Channels per port

- Eight Traffic Classes per port

- Fixed and Round-Robin Virtual

- 5 Standard Hot-Plug Controllers

- Upstream port as hot-plug client

- Transaction Layer end-to-end CRC

- Poison bit

- Advanced Error Reporting

- Lane Status bits and GPO available

- Per port error diagnostics

(hot-plug)

for Multi-Host or Intelligent I/O

Support

ports (x1, x2, x4, or x8)

EEPROM, I

L0s, L1, L2/L3 Ready, L2 and L3

Channel Port Arbitration

• Bad DLLPs

• Bad TLPs

• CRC errors

JTAG boundary scan

Fatal Error out-of-band signal option

Version 1.6 2007

C, or Host software

Multi-purpose, Feature Rich ExpressLane™ PCI Express Switch

The ExpressLane PEX 8518 device offers PCI Express switching capability

enabling users to add scalable high bandwidth, non-blocking interconnection

to a wide variety of applications including servers, storage systems,

communications platforms, blade servers, and embedded-control

products. The PEX 8518 is well suited for fan-out, aggregation, peer-to-

peer, and intelligent I/O module applications.

Highly Flexible Port Configurations

The PEX 8518 offers highly configurable ports. There are a maximum of five

ports that can be configured to any legal width from x1 to x8, in any

combination to support your specific bandwidth needs. The ports can be

configured for symmetric (each port having the same lane width and traffic

load) or asymmetric (ports having different lane widths) traffic. In the event

of asymmetric traffic, the PEX 8518 features a flexible central packet

memory that allocates a memory buffer for each port as required by the

application or endpoint. This buffer allocation along with the device's

flexible packet flow control minimizes bottlenecks when the upstream and

aggregated downstream bandwidths do not match (are asymmetric). Any of

the ports can be designated as the upstream port, which can be changed

dynamically.

End-to-end Packet Integrity

The PEX 8518 provides end-to-end CRC protection (ECRC) and Poison bit

support to enable designs that require guaranteed error-free packets. These

features are optional in the PCI Express specification, but PLX provides

them across its entire ExpressLane switch product line.

Non-Transparent “Bridging” in a PCI Express Switch

The PEX 8518 supports full non-transparent bridging (NTB) functionality to

allow implementation of multi-host systems and intelligent I/O modules in

applications such as communications, storage, and blade servers. To

ensure quick product migration, the non-transparency features are

implemented in the same fashion as in standard PCI applications.

Non-transparent bridges allow systems to isolate memory domains by

presenting the processor subsystem as an endpoint, rather than another

memory system. Base address registers are used to translate addresses;

doorbell registers are used to send interrupts between the address domains;

and scratchpad registers are accessible from both address domains to allow

inter-processor communication.

Two Virtual Channels

The ExpressLane PEX 8518 switch supports two full-featured Virtual

Channels (VCs) and eight Traffic Classes (TCs). The mapping of Traffic

Classes to port-specific Virtual Channels allows for different mappings for

different ports. In addition, the devices offer user-selectable Virtual Channel

arbitration algorithms to enable users to fine tune the Quality of Service

(QoS) required for a specific application.

Flexible & Versatile PCI Express

PEX 8518

Switch

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