IDT7130SA25JI Integrated Device Technology, Inc., IDT7130SA25JI Datasheet
IDT7130SA25JI
Manufacturer Part Number
IDT7130SA25JI
Description
PLCC-52
Manufacturer
Integrated Device Technology, Inc.
Datasheet
1.IDT7130LA35JI.pdf
(18 pages)
Specifications of IDT7130SA25JI
Date_code
03+
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I/O
NOTES:
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.
2. Open drain output: requires pullup resistor.
©2000 Integrated Device Technology, Inc.
0L
High-speed access
– Military: 25/35/55/100ns (max.)
– Industrial: 55/100ns (max.)
– Commercial: 20/25/35/55/100ns (max.)
Low-power operation
– IDT7130/IDT7140SA
—
—
– IDT7130/IDT7140LA
—
—
MASTER IDT7130 easily expands data bus width to 16-or-
more-bits using SLAVE IDT7140
IDT7140 (SLAVE): BUSY is input.
BUSY
- I/O
R/W
Active: 550mW (typ.)
Standby: 5mW (typ.)
Active: 550mW (typ.)
Standby: 1mW (typ.)
INT
OE
CE
A
A
7L
9L
0L
L
L
L
L
L
(1,2)
(2)
Decoder
Address
R/W
OE
CE
L
L
L
10
HIGH SPEED
1K X 8 DUAL-PORT
STATIC SRAM
Control
I/O
ARBITRATION
INTERRUPT
MEMORY
ARRAY
LOGIC
and
1
On-chip port arbitration logic (IDT7130 Only)
BUSY output flag on IDT7130; BUSY input on IDT7140
INT flag for port-to-port communication
Fully asynchronous operation from either port
Battery backup operation–2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Available in 48-pin DIP and LCC, 52-pin PLCC, and 64-pin
STQFP and TQFP
Control
I/O
10
Address
Decoder
R/W
CE
OE
R
R
R
IDT7130SA/LA
IDT7140SA/LA
2689 drw 01
OE
CE
R/W
I/O
BUSY
A
A
INT
DSC-2689/10
9R
0R
R
0R
R
R
R
(2)
-I/O
R
(1,2)
7R
,
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