IDT7025S20PFI Integrated Device Technology, Inc., IDT7025S20PFI Datasheet
IDT7025S20PFI
Manufacturer Part Number
IDT7025S20PFI
Description
TQFP100
Manufacturer
Integrated Device Technology, Inc.
Datasheet
1.IDT7025S20PFI.pdf
(21 pages)
Specifications of IDT7025S20PFI
Date_code
09+
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
©2000 Integrated Device Technology, Inc.
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
Low-power operation
– IDT7025S
– IDT7025L
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
Active: 750mW (typ.)
Standby: 5mW (typ.)
Active: 750mW (typ.)
Standby: 1mW (typ.)
I/O
I/O
8L
0L
BUSY
-I/O
-I/O
SEM
R/W
A
INT
UB
CE
OE
LB
A
12L
15L
0L
7L
L
L
L
L
L
L
L
L
(1,2)
(2)
Decoder
Address
R/W
OE
CE
L
L
L
HIGH-SPEED
8K x 16 DUAL-PORT
STATIC RAM
13
Control
I/O
ARBITRATION
SEMAPHORE
INTERRUPT
MEMORY
ARRAY
LOGIC
M/S
1
IDT7025 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin
Quad Flatpack
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Control
I/O
13
Decoder
Address
CE
OE
R/W
R
R
R
2683 drw 01
IDT7025S/L
R/W
LB
CE
OE
I/O
I/O
BUSY
A
A
SEM
UB
INT
12R
0R
R
8R
0R
R
R
R
R
R
R
(2)
-I/O
-I/O
R
(1,2)
15R
7R
DSC 2683/8
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