74ALVC162240TX Fairchild Semiconductor, 74ALVC162240TX Datasheet

74ALVC162240TX

Manufacturer Part Number

74ALVC162240TX

Description

IC INVERTER DUAL 8-INPUT 48TSSOP

Manufacturer

Fairchild Semiconductor

Series

74ALVCr

Datasheet

1.74ALVC162240T.pdf (6 pages)

Specifications of 74ALVC162240TX

Logic Type

Inverter

Number Of Inputs

Number Of Circuits

Current - Output High, Low

12mA, 12mA

Voltage - Supply

1.65 V ~ 3.6 V

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

48-TSSOP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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74ALVC162240T

74ALVC162240

Low Voltage 16-Bit Inverting Buffer/Line Driver

with 3.6V Tolerant Inputs and Outputs

and 26 Series Resistors in Outputs

General Description

The ALVC162240 contains sixteen inverting buffers with

3-STATE outputs to be employed as a memory and

address driver, clock driver, or bus oriented transmitter/

receiver. The device is nibble (4-bit) controlled. Each nibble

has separate 3-STATE control inputs which can be shorted

together for full 16-bit operation.

The 74ALVC162240 is designed for low voltage (1.65V to

3.6V) V

74ALVC162240 is also designed with 26

in the outputs. This design reduces line noise in applica-

tions such as memory address drivers, clock drivers, and

bus transceivers/transmitters.

The 74ALVC162240 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Order Number

applications with I/O capability up to 3.6V. The

Package Number

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

series resistors

DS500699

Features

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

value of the resistor is determined by the current-sourcing capability of the

driver.

Pin Descriptions

1.65V to 3.6V V

3.6V tolerant inputs and outputs

26 series resistors in outputs

Power-off high impedance inputs and outputs

Supports live insertion and withdrawal (Note 1)

Uses patented noise/EMI reduction circuitry

Latchup conforms to JEDEC JED78

ESD performance:

Pin Names

3.8 ns max for 3.0V to 3.6V V

4.3 ns max for 2.3V to 2.7V V

7.6 ns max for 1.65V to 1.95V V

Human body model

Machine model

Package Descriptions

–I

–O

supply operation

Output Enable Input (Active LOW)

200V

2000V

through a pull-up resistor; the minimum

November 2001

Revised November 2001

Description

Outputs

Inputs

www.fairchildsemi.com

Related parts for 74ALVC162240TX

74ALVC162240TX Summary of contents

Page 1

... MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © 2001 Fairchild Semiconductor Corporation Features 1.65V to 3.6V V supply operation CC 3 ...

Page 2

Connection Diagram Functional Description The 74ALVC162240 contains sixteen inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 3) 0. Input Diode Current ( Output Diode Current (I ) ...

Page 4

AC Electrical Characteristics Symbol Parameter V CC Min Propagation Delay PHL PL 1.3 Bus to Bus Output Enable Time 1.3 PZL PZH Output Disable Time 1.3 PLZ PHZ Capacitance Symbol Parameter ...

Page 5

AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics: f Symbol 3.3V 0. FIGURE 2. Waveform for Inverting and ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

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