AS7C4096A15JIN Alliance Semiconductor, AS7C4096A15JIN Datasheet

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AS7C4096A15JIN

Manufacturer Part Number
AS7C4096A15JIN
Description
SOJ
Manufacturer
Alliance Semiconductor
Datasheet

Specifications of AS7C4096A15JIN

Date_code
04+
Logic block diagram
February 2006
Features
• Pin compatible to AS7C4096
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
• Low power consumption: ACTIVE
• Low power consumption: STANDBY
Selection guide
GND
Maximum address access time
Maximum outputenable access time
Maximum operating current
Maximum CMOS standby current
- 10/12/15/20 ns address access time
- 5/6 ns output enable access time
- 880mW/max @ 10 ns
- 55mW/max CMOS
2/21/06, v 1.2
V
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CC
Column decoder
524,288 × 8
(4,194,304)
Input buffer
Array
Control
Circuit
5.0V 512K × 8 CMOS SRAM
Alliance Semiconductor
WE
OE
CE
I/O1
I/O8
Pin arrangement
• Equal access and cycle times
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
–10
160
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
10
10
5
I/O1
I/O2
GND
I/O3
I/O4
V
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CE
CC
®
36-pin SOJ (400 mil)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
–12
140
10
12
6
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
s
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
V
I/O6
I/O5
A14
A13
A12
A11
A10
NC
CC
–15
120
15
10
6
Copyright © Alliance Semiconductor. All rights reserved.
I/O1
I/O2
I/O3
I/O4
GND
V
WE
A5
A6
A7
A8
A9
A0
A1
A2
A3
A4
CE
NC
NC
NC
NC
CC
44-pin TSOP 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
AS7C4096A
–20
100
20
10
6
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
P. 1 of 10
NC
NC
A18
A17
A16
A15
A14
A13
A12
A11
A10
NC
NC
OE
I/O8
I/O7
GND
V
I/O6
I/O5
NC
NC
Unit
mA
mA
CC
ns
ns

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