W986416CH-8H Winbond, W986416CH-8H Datasheet

W986416CH-8H

Manufacturer Part Number

W986416CH-8H

Description

Manufacturer

Winbond

Datasheet

1.W986416CH-8H.pdf (42 pages)

Specifications of W986416CH-8H

Case

TSOP54

Date_code

2006+

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

W986416CH-8H

Manufacturer:

WINBOND/华邦

Quantity:

20 000

Company:

H&T Electronics

Part Number:

W986416CH-8H

Quantity:

55 000

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Features

General Description

16 bits. Using pipelined architecture and 0.20um process technology, W986416CH delivers a data bandwidth of up to 332M

bytes per second (-6). For different application, W986416CH is sorted into four speed grades: -6, -7, -75 and -8H. The -6 parts

can run up to 166Mhz/CL3. The -7 parts can run up to 143Mhz/CL3 specification. The -75 parts can run up to PC133/CL3

specification. The -8H parts can run up to 125Mhz/CL3 or PC100/CL2 specification.

1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated

by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock

cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.

to maximize its performance. W986416CH is ideal for main memory in high performance applications.

Key Parameters

Revision 1.2

Symbol

RCD

CC1

CC4

CC6

W986416CH is a high speed synchronous dynamic random access memory (SDRAM), organized as 1M words x 4 banks x

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of

By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst

3.3V 0.3V power supply

Up to 166 MHz clock frequency

1,048,576 words x 4 banks x 16 bits organization

Auto Refresh and Self Refresh

CAS latency: 2 and 3

Burst Length: 1, 2, 4, 8 , and full page

Burst read, Single Writes Mode

Byte data controlled by UDQM and LDQM

Power-Down Mode

Auto-Precharge and controlled precharge

4k refresh cycles / 64ms

Interface: LVTTL

Package: TSOP II 54 pin, 400 mil - 0.80

Clock Cycle Time

Access Time from CLK

Precharge to Active Command

Active to Read/Write Command

Operation Current ( Single bank )

Burst Operation Current

Self-Refresh Current

Description

min/max

max

min

- 1 -

1M x 16 bit x 4 Banks SDRAM

130mA

80mA

18ns

1mA

6ns

5ns

-6

Publication Release Date: June, 1999

115mA

65mA

5.4ns

20ns

1mA

7ns

-7

-75(PC133)

W986416CH

115mA

65mA

7.5ns

5.4ns

20ns

1mA

-8H(PC100)

110mA

60mA

20ns

1mA

8ns

6ns

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