AM29LV6402MH100RPHI AMD [Advanced Micro Devices], AM29LV6402MH100RPHI Datasheet
AM29LV6402MH100RPHI
Related parts for AM29LV6402MH100RPHI
AM29LV6402MH100RPHI Summary of contents
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Data Sheet This product has been retired and is not available for designs. For new and current designs, S29GL128N supersedes Am29LV6402M and is the factory-recommended migration path. Please refer to the S29GL128N Data Sheet for specifications and ordering information. Availability ...
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Am29LV6402M 128 Megabit ( 32-Bit 16-Bit) MirrorBit™ 3.0 Volt-only Uniform Sector Flash Memory with Versatile I/O™ Control This product has been retired and is not available for designs. For new and current designs, S29GL128N supersedes Am29LV6402M ...
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GENERAL DESCRIPTION The Am29LV6402M consists of two 64 Mbit, 3.0 volt single power supply flash memory devices and is or- ganized as 4,194,304 doublewords or 8,388,608 words. The device has a 32-bit wide data bus that can also function as ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 MCP Block Diagram . . . . . . . . . ...
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PRODUCT SELECTOR GUIDE Part Number Speed Option V = 3.0–3 Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page access time (t ) PACC Max. OE# Access Time (ns) MCP BLOCK DIAGRAM A21 to A0 RY/BY# ...
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FLASH MEMORY BLOCK DIAGRAM RY/BY RESET# WE# State WP#/ACC Control WORD# Command Register CE# OE# V Detector CC A21–A0 Note:In x16 Mode, DQ31 and DQ23 must be connected together on the board. January 23, 2006 Sector ...
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CONNECTION DIAGRAMS DQ21 DQ28 RFU DQ23/A-1 A13 A12 DQ30 WE# RESET RY/BY# WP#/ACC DQ31/A-1 A7 A17 ...
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PIN CONFIGURATION A –1 = Least significant address bit for the 16-bit data bus, and selects between the high and low word. A –1 is not used for the 32-bit mode (WORD A21–A0 = 22-bit address bus for ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: H 100R PH Am29LV6402M DEVICE NUMBER/DESCRIPTION Am29LV6402MH Megabit (4 ...
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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch ...
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Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins control and selects the device. OE# is the output con- trol and gates array data to ...
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CE# and RESET# are held ± 0.3 V, the device will be in the standby mode, CC but the standby current will be greater. The device re- quires standard access time (t CE ...
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A21–A15 Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 0 0 ...
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Table 2. Sector Address Table (Continued) A21–A15 Sector SA47 SA48 SA49 SA50 SA51 SA52 SA53 0 ...
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Table 2. Sector Address Table (Continued) A21–A15 Sector SA95 SA96 SA97 SA98 SA99 SA100 SA101 1 ...
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Autoselect Mode The autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equip- ment to automatically match a device to be pro- grammed with ...
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Sector Group Protection and Unprotection The hardware sector group protection feature disables both program and erase operations in any sector group. In this device, a sector group consists of four adjacent sectors that are protected or unprotected at the same ...
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Write Protect (WP#) The Write Protect function provides a hardware method of protecting the first or last sector without using V . Write Protect is one of two functions pro- ID vided by the WP#/ACC input. If the system asserts ...
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START PLSCNT = 1 RESET Wait 1 μs Temporary Sector No First Write Group Unprotect Cycle = 60h? Mode Yes Set up sector group address Sector Group Protect: Write 60h to sector group address with A6 = ...
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SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 128 doublewords/256 words in length, and uses ...
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START START If data = 00h, If data = 00h, RESET# = RESET# = SecSi Sector is SecSi Sector unprotected. unprotected. If data = 01h, If data = 01h, ...
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Addresses (x32) Data 10h 00005151h 11h 00005252h 12h 00005959h 13h 00000202h 14h 00000000h 15h 00004040h 16h 00000000h 17h 00000000h 18h 00000000h 19h 00000000h 1Ah 00000000h Addresses (x16) Data 1Bh 00002727h 1Ch 00003636h 1Dh 00000000h 1Eh 00000000h 1Fh 00000707h 20h 00000707h ...
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Addresses (x16) Data 27h 00001717h 28h 00000101h 29h 00000000h 2Ah 00000505h 2Bh 00000000h 2Ch 00000101h 2Dh 00007F7Fh 2Eh 00000000h 2Fh 00000000h 30h 00000101h 31h 00000000h 32h 00000000h 33h 00000000h 34h 00000000h 35h 00000000h 36h 00000000h 37h 00000000h 38h 00000000h 39h ...
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Table 9. Primary Vendor-Specific Extended Query Addresses (x16) Data 40h 00005050h 41h 00005252h 42h 00004949h 43h 00003131h 44h 00003333h 45h 000000808h 46h 000000202h 47h 00000101h 48h 00000101h 49h 00000404h 4Ah 00000000h 4Bh 00000000h 4Ch 00000101h 4Dh 0000B5B5h 4Eh 0000C5C5h 00000404h/ ...
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COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Tables 10 and 11 define the valid register command sequences. Writing incorrect address and data values or writing them in the ...
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Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing an 8-doubleword/16-word random Elec- tronic Serial Number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector ...
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Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. The host ...
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Write “Write to Buffer” command and Sector Address Write number of addresses to program minus 1(WC) and Sector Address Write first address/data Yes Abort Write to Buffer Operation? (Note 1) Write next address/data pair WC = ...
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Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Tables 10 and 11 for program command sequence. Figure 5. Program Operation Program Suspend/Program Resume Command ...
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Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip ...
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After the erase operation has been suspended, the device enters the erase-suspend-read mode. The sys- tem can read data from or program data to any sector not selected for erasure. (The device “erase sus- pends” all sectors selected for erasure.) ...
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Command Definitions Table 10. Command Definitions (x32 Mode, WORD Command Sequence (Note 1) Addr Read (Note 6) 1 Reset (Note 7) 1 Manufacturer ID 4 Device ID (Note 9) 6 SecSi TM Sector Factory Protect 4 (Note 10) ...
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Table 11. Command Definitions (x16 Mode, WORD Command Sequence (Note 1) Addr Read (Note 6) 1 Reset (Note 7) 1 Manufacturer ID 4 Device ID (Note SecSi Sector Factory Protect 4 (Note 10) Sector Protect ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2 and DQ10, DQ3 and DQ11, DQ5 and DQ13, DQ6 and DQ14, and DQ7 and DQ15. Table 12 and the following subsections ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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START Read DQ7–DQ0 Read DQ7–DQ0 No Toggle Bit = Toggle? Yes No DQ5 = 1? Yes Read DQ7–DQ0 Twice Toggle Bit No = Toggle? Yes Program/Erase Operation Not Program/Erase Complete, Write Operation Complete Reset Command Note: The system should recheck ...
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The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 and/or DQ13 has not gone high. The system may continue to monitor the toggle bits and DQ5 and DQ13 through successive read ...
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DQ1: Write-to-Buffer Abort DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 and DQ9 “ 1 ” ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied ...
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DC CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol (Notes) I Input Load Current ( A9, ACC Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 ( Initial Page ...
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TEST CONDITIONS Device Under Test C 6.2 kΩ L Note: Diodes are IN3064 or equivalent. Figure 12. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0 Table 13. Test ...
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AC CHARACTERISTICS Read-Only Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV CE t Page Access Time PACC t ...
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AC CHARACTERISTICS A21-A2 A1-A0* Data Bus CE# OE# * Figure shows doubleword mode. Addresses are A1–A-1 for word mode. 42 Same Page PACC PACC t ACC Qa Qb Figure 15. Page Read Timings Am29LV6402M Ad Ac ...
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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std. RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read Mode (See Note) t RESET# Pulse Width RP ...
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AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low during toggle bit polling ASO t t ...
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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Notes program address program data Illustration shows device in word ...
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AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE Data 55h RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid ...
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AC CHARACTERISTICS t RC Addresses VA t ACC OE# t OEH WE# DQ7 DQ0–DQ6 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read ...
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AC CHARACTERISTICS Addresses CE# t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6 and DQ14. Illustration shows first two status cycle after command sequence, last status read cycle, and array ...
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AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR ID RESET# Setup Time for Temporary Sector t RSP Unprotect 1. Not 100% tested Specifications are tested with V =V ...
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AC CHARACTERISTICS RESET# SA, A6, A1, A0 Sector Group Protect or Unprotect Data 60h 1 µs CE# WE# OE# * For sector group protect For sector group ...
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AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time ELAX Data Setup ...
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AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes: 1. Figure indicates last two bus cycles of a program or erase operation ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Single Doubleword/Word Program Time (Note 3) Accelerated Single Doubleword/ Word Program Time Total Write Buffer Program Time (Note 4) Effective Write Buffer Program Time (Note 3) Total Accelerated Write ...
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PHYSICAL DIMENSIONS LSB080—80-Ball Fortified Ball Grid Array (Fortified BGA Package D 0.20 C (2X) INDEX MARK PIN A1 10 CORNER TOP VIEW SIDE VIEW 6 b 80X 0. 0.10 ...
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REVISION SUMMARY Revision A (January 20, 2003) Initial release. Revision B (September 17, 2003) Global Changed data sheet status from Advance Information to Preliminary. Distinctive Characteristics Changed description of device erase cycle endurance. Changed typical sector erase time, typical write ...