AM29LV320MB SPANSION [SPANSION], AM29LV320MB Datasheet - Page 33

• Manufacturer Part Number: AM29LV320MB
• Manufacturer: SPANSION [SPANSION]

Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Tables
13
chip erase command sequence. Note that the Secured
Silicon Sector, autoselect, and CFI functions are un-
available when a program operation is in progress.
When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, or DQ2.
Refer to the
mation on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
26518C3 January 31, 2007
No
Figure 6. Program Suspend/Program Resume
shows the address and data requirements for the
Sequence in Progress
Program Operation
Write address/data
Write address/data
Program Suspend
or Write-to-Buffer
operation prior to
Device reverts to
Read data as
Wait 15 μs
XXXh/B0h
XXXh/30h
reading?
required
Done
Write Operation Status
Yes
Write Program Suspend
Command Sequence
Command is also valid for
Erase-suspended-program
operations
Autoselect operations are also allowed
Data cannot be read from erase- or
program-suspended sectors
Write Program Resume
Command Sequence
section for infor-
D A T A
12
Am29LV320MT/B
and
S H E E T
curs, the chip erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 7
tion. Refer to the
bles in the AC Characteristics section for parameters,
and
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command. Tables
the address and data requirements for the sector
erase command sequence. Note that the Secured Sili-
con Sector, autoselect, and CFI functions are unavail-
able when a program operation is in progress.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase ad-
dress and command following the exceeded time-out
may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to en-
sure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or
Erase Suspend during the time-out period resets
the device to the read mode. The system must re-
write the command sequence and any additional ad-
dresses and commands.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by reading DQ7, DQ6, or
DQ2 in the erasing sector. Refer to the
tion Status
Figure 19
illustrates the algorithm for the erase opera-
section for information on these status bits.
section for timing diagrams.
Erase and Program Operations
12
and
Write Opera-
13
shows
31
ta-