AM29LV081B-90EE AMD [Advanced Micro Devices], AM29LV081B-90EE Datasheet - Page 10
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AM29LV081B-90EE
Manufacturer Part Number
AM29LV081B-90EE
Description
8 Megabit (1 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM29LV081B-90EE.pdf
(40 pages)
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nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the Autoselect Mode and Autoselect
Command Sequence sections for more information.
I
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range than
V
V
the standby current will be greater. The device requires
standard access time (t
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
When the RESET# input is held at V
vice enters the standby mode within a period of t
tristates all data output pins, and ignores all read/write
attempts for the duration of the RESET# pulse. This
mode is “RESET# controlled,” since CE# is don’t care
under this condition. Once the RESET# pin is set
high, the device requires t
tion to t
also terminates any operation in progress and resets
the device.
I
standby current specification.
8
CC2
CC3
IH
CC
.) If CE# and RESET# are held at V
± 0.3 V, the device will be in the standby mode, but
in the DC Characteristics table represents the ac-
in the DC Characteristics table represents the
CE
access time for reading data. This method
CE
RH
) for read access when the
of wake up time in addi-
SS
IH
± 0.3 V, the de-
, but not within
CC
± 0.3 V.
D A T A S H E E T
Am29LV081B
RPD
CC
,
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for t
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I
Characteristics table represents the automatic sleep
mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
system can thus monitor RY/BY# to deter mine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is
completed within a time of t
ded Algorithms). The system can read data t
the RESET# pin returns to V
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high imped-
ance state.
IL
but not within V
READY
(during Embedded Algorithms). The
SS
±0.3 V, the standby current will
21525D6 October 12, 2006
IH
READY
, output from the device is
IH
.
CC4
SS
(not during Embed-
). If RESET# is held
±0.3 V, the device
CC4
in the DC
ACC
RH
RP
, the
after
+ 30