FM1808-120-P ETC [List of Unclassifed Manufacturers], FM1808-120-P Datasheet - Page 2

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FM1808-120-P

Manufacturer Part Number
FM1808-120-P
Description
256Kb Bytewide FRAM Memory
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet
Ramtron
Figure 1. Block Diagram
Pin Description
Functional Truth Table
27 July 2000
Pin Name
A0-A14
DQ0-7
/CE
/OE
/WE
VDD
VSS
/CE
H
æ
L
L
WE
CE
OE
Pin Number
1-10, 21, 23-26
11-13, 15-19
20
22
27
28
14
/WE
X
X
H
L
A0-A14
Address
/OE
X
X
L
X
Latch
Control
Logic
I/O
I
I/O
I
I
I
I
I
Pin Description
Address. The 15 address lines select one of 32,768 bytes in the FRAM
array. The address value will be latched on the falling edge of /CE.
Data. 8-bit bi-directional data bus for accessing the FRAM array.
Chip Enable. /CE selects the device when low. The falling edge of /CE
causes the address to be latched internally. Address changes that
occur after /CE goes low will be ignored until the next falling edge
occurs.
Output Enable. When /OE is low the FM1808 drives the data bus when
valid data is available. Taking /OE high causes the DQ pins to be tri-
stated.
Write Enable. Taking /WE low causes the FM1808 to write the contents
of the data bus to the address location latched by the falling edge of
/CE.
Supply Voltage. 5V
Ground.
A10-A14
A0-A7
A8-A9
Function
Standby/Precharge
Latch Address
Read
Write
Decoder
Row
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
Column Decoder
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
Block Decoder
Bus Driver
I/O Latch
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
1Kx8
DQ0-7
FM1808-70
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