EVAL-AD9388AFEZ_1 AD [Analog Devices], EVAL-AD9388AFEZ_1 Datasheet
EVAL-AD9388AFEZ_1
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EVAL-AD9388AFEZ_1 Summary of contents
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FEATURES Mutliformat decoder Three 10-bit analog-to-digital converters (ADCs) ADC sampling rates up to 170 MHz Mux with 12 analog input channels 525i-/625i-component SD support 525p-/625p-component progressive scan support 720p-/1080i-/1080p-component HDTV support Digitizes RGB graphics up to 1600 × 1200 at ...
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... Added Figure 6 ................................................................................ 13 Added Table 7 .................................................................................. 13 Changes to Component Processor Pixel Data Output Modes Section .............................................................................................. 16 Changes to Component Processor (CP) Section........................ 17 Added AD9388A/ADV7441A Evaluation Platform Section .... 24 Changes to Ordering Guide .......................................................... 25 10/07—Revsion Sp0: Initial Version Component Processor Pixel Data Output Modes .................. 16 Component Video Processing .................................................. 16 RGB Graphics Processing ......................................................... 16 General Features ...
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FUNCTIONAL BLOCK DIAGRAM FORMATTER OUTPUT Figure 1. Rev Page AD9388A 06915-001 DDCB_SCL DDCB_SDA DDCA_SDA DDCA_SCL ...
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AD9388A SPECIFICATIONS ELECTRICAL CHARACTERISTICS AVDD = 1. 1.89 V, DVDD = 1. 1.98 V, DVDDIO = 2. 3.63 V, PVDD = 1. 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD ...
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Parameter Symbol TMDS PLL and Equalizer Supply Current Analog Supply Current I AVDD Terminator Supply Current I TVDD Audio and Video Supply Current I PVDD Power-Down Current I PWRDN Power-Up Time t PWRUP 1 The minimum/maximum specifications are guaranteed ...
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AD9388A ANALOG AND HDMI SPECIFICATIONS AVDD = 1. 1.89 V, DVDD = 1. 1.98 V, DVDDIO = 2. 3.63 V, PVDD = 1. 1.89 V, TVDD = 3.135 V to 3.465 V, ...
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DATA AND I C TIMING CHARACTERISTICS AVDD = 1. 1.89 V, DVDD = 1. 1.98 V, DVDDIO = 2. 3.63 V, PVDD = 1. 1.89 V, TVDD = 3.135 V to ...
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AD9388A Timing Diagrams t 3 xDA xCL NOTES 1. THE PREFIX x REFERS TO PIN NAMES BEGINNING WITH S, DDCA_S, AND DDCB_S. LLC P0 TO P29, VS, HS, FIELD/ SCLK LRCLK t 16 I2Sx ...
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ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating AVDD to AGND 2.2 V DVDD to DGND 2.2 V PVDD to PGND 2.2 V DVDDIO to DGND 4 V CVDD to CGND 2.2 V TVDD to TGND 4 V DVDDIO to AVDD ...
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AD9388A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DDCB_SDA 1 SPDIF 2 PIN 1 I2S0 3 I2S1 4 I2S2 5 I2S3 6 LRCLK 7 SCLK 8 MCLKOUT 9 EXT_CLAMP 10 SDA 11 SCL 12 ALSB 13 DGND 14 DVDDIO 15 DE/FIELD 16 ...
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Pin No. Mnemonic P29 INT1 20 SYNC_OUT/INT2 17 HS/CS 18 VS/FIELD 16 DE/FIELD 11 SDA 12 SCL 13 ALSB 21 RESET 51 LLC 65 XTAL1 ...
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AD9388A Pin No. Mnemonic 121 RXA_2N 122 RXA_2P 128 RXB_CN 129 RXB_CP 131 RXB_0N 132 RXB_0P 134 RXB_1N 135 RXB_1P 137 RXB_2N 138 RXB_2P 106 DDCA_SDA 1 DDCB_SDA 105 DDCA_SCL 144 DDCB_SCL 2 SPDIF 3 I2S0 4 I2S1 5 I2S2 ...
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TEST6 1 SPDIF 2 PIN 1 I2S0 3 I2S1 4 I2S2 5 I2S3 6 LRCLK 7 SCLK 8 MCLKOUT 9 EXT_CLAMP 10 SDA 11 SCL 12 ALSB 13 DGND 14 DVDDIO 15 DE/FIELD 16 HS/CS 17 VS/FIELD 18 INT1 19 ...
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AD9388A Pin No. Mnemonic P29 INT1 20 SYNC_OUT/INT2 17 HS/CS 18 VS/FIELD 16 DE/FIELD 11 SDA 12 SCL 13 ALSB 21 RESET 51 LLC 65 ...
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Pin No. Mnemonic 2 SPDIF 3 I2S0 4 I2S1 5 I2S2 6 I2S3 7 LRCLK 8 SCLK 9 MCLKOUT 10 EXT_CLAMP 48 EXT_CLK 124 RTERM ground power input, and O = output. 1 ...
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AD9388A FUNCTIONAL OVERVIEW The following overview provides a brief description of the functionality of the AD9388A. More details are available in the Theory of Operation section. ANALOG FRONT END The analog front end of the AD9388A provides three high quality ...
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THEORY OF OPERATION ANALOG FRONT END The AD9388A analog front end comprises three 10-bit ADCs that digitize the analog video signal before applying it to the CP. The analog front end uses differential channels to each ADC to ensure high ...
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AD9388A PIXEL OUTPUT FORMATTING Note that unused pins of the pixel output port are driven with a low voltage. Table 8. Component Processor Pixel Output Pin Map (P19 toP0) 1 Processor Mode/Format CP Mode 1 Video output 2 8-bit 4:2:2 ...
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Processor Mode/Format CP Mode 17 Video output 30-bit 4:4:4 CP Mode 18 Video output 30-bit 4:4:4 CP Mode 19 Video output 30-bit 4:2 processor uses digitizer or HDMI as input. 2 Maximum pixel clock rate of 54 ...
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AD9388A 1 Processor Mode/Format 29 CP Mode 14 Video output 3, 4 24-bit 4:4:4 CP Mode 15 Video output 24-bit 4:4 Mode 16 Video output 30-bit 4:4 Mode 17 Video output 30-bit 4:4:4 3, ...
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REGISTER MAP ARCHITECTURE The AD9388A registers are controlled via a 2-wire serial ( address. The state of the ALSB pin (Pin 13) sets Bit 2 of each register map address in Table 10. Table 10. AD9388A Map ...
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AD9388A TYPICAL CONNECTION DIAGRAM Figure 8. Typical Connection Diagram Rev Page ...
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RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS Note that the external loop filter components for the ELPF and AUDIO_ELPF pins should be placed as close as possible to the respective pins. The recommended component values are specified in Figure 9 and Figure ...
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... AD9742s (12-bit DACs) from Analog Devices. This allows the user to drive a VGA monitor with just the motherboard and front-end board. Table 11. Front-End Modular Board Details Front-End Modular Board Model EVAL-ADV7441AFEZ_1 EVAL-ADV7441AFEZ_2 EVAL-AD9388AFEZ_1 EVAL-AD9388AFEZ_2 EVAL-AD9388AFEZ_3 VIDEO INPUT BOARD EVAL-AD9388AFEZ_x OR EVAL-ADV7441AFEZ_x AD9388A/ADV7441A DECODER ...
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... AD9388ABSTZ-170 1, 2 AD9388ABSTZ-110 AD9388ABSTZ AD9388ABSTZ- EVAL-AD9388AFEZ_1 EVAL-AD9388AFEZ_2 EVAL-AD9388AFEZ_3 RoHS Compliant Part. 2 This part is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection, LLC for licensing requirements) to purchase any components with internal HDCP keys. ...
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AD9388A NOTES Rev Page ...
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NOTES Rev Page AD9388A ...
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AD9388A NOTES ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06915-0-7/08(B) Rev Page ...