GS9004CCKB GENNUM [Gennum Corporation], GS9004CCKB Datasheet - Page 3

• Manufacturer Part Number: GS9004CCKB
• Description: Serial Digital Cable Equalizer
• Manufacturer: GENNUM [Gennum Corporation]

V
The GS9004C Cable Equalizer is a bipolar integrated circuit
used to equalize SMPTE 259M signals from a co-axial cable.
The device is implemented as a fourteen pin SOIC, powered
from a single five volt supply. With an operating frequency up
to 400 Mb/s, the equalizer consumes about 285 mW of
power.
The Serial Digital signal is connected to the input (pins 8, 9)
either differentially or single ended with the unused input
being decoupled. The equalized signal is generated by
passing the cable signal through a voltage variable filter
having a characteristic which closely matches the inverse
cable loss characteristic. Additionally, the variation of the filter
characteristic with control voltage is designed to imitate the
variation of the inverse cable loss characteristic as the cable
length is varied.
The amplitude of the equalized signal is monitored by a peak
detector circuit which produces an output current with a
polarity corresponding to the difference between the desired peak
signal level and the actual peak signal level.
CC
50
OEM
100n
100n
V
CC
SSI
V
100n
100n
CC
V
V
CC
CC
100n
+
10
100n
TEKTRONIX
GS9004C CABLE EQUALIZER - DETAILED DEVICE DESCRIPTION
ANRITSU
ME522A
TSG422
OR
1
2
3
4
5
6
7
V
V
OEM
V
N/C
SSI
AGC
CC
CC
CC
GS9004C
GND1
DATA
DATA
GND
GND
DRIVER
CABLE
IN -
IN+
47p
14
13
12
11
10
9
8
SDI
75
DATA
CLOCK
75
GND
+5V
113
680
Fig. 1 Test Circuit
680
Fig. 2 Test Set-up 1
8281 CABLE
100
100
18n
47p
10
OEM
3
+
This output is integrated by an external AGC filter capacitor
(AGC CAP pin 7), providing a steady control voltage for the
voltage variable filter.
A separate signal strength indicator output, (SSI pin 6),
proportional to the amount of AGC, is also provided. As the
filter characteristic is varied automatically by the application of
negative feedback, the amplitude of the equalized signal is
kept at a constant level which is representative of the original
amplitude at the transmitter.
The equalized signal is then DC restored, effectively restoring
the logic threshold of the equalized signal to its correct level
irrespective of shifts due to AC coupling.
As the final stage of signal conditioning, a comparator converts
the analog output of the DC restorer to a regenerated digital
output signal having pseudo-ECL voltage levels. These outputs,
DATA and DATA, are available from pins 13 and 14 respectively.
An OUTPUT 'EYE' MONITOR (pin 3) allows verification of
signal integrity after equalization, prior to reslicing.
D.U.T.
100n
V
5
6
7
8
V
CC
CC
All resistors in ohms, all capacitors in microfarads,
all inductors in henries unless otherwise stated.
GND
SI
SI
VCC
GS9007
CABLE
DRIVER
SO2
SO2
SO1
SO1
4
3
2
1
OSCILLOSCOPE
VERTICAL
150
TRIGGER
150
IN
150
IN
150
1.0
1.0
1.0
1.0
1.8p
68
1.8p
68
68
1.8p
1.8p
68
521 - 72 - 00
SDO2
SDO1
SDO4
SDO3