ADIS16201/PCB AD [Analog Devices], ADIS16201/PCB Datasheet - Page 5

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ADIS16201/PCB

Manufacturer Part Number
ADIS16201/PCB
Description
Programmable Dual-Axis
Manufacturer
AD [Analog Devices]
Datasheet
TIMING SPECIFICATIONS
T
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
1
TIMING DIAGRAMS
SCLK
DATARATE
DATARATE
cs
DAV
DSU
DHD
DF
DR
SFS
Guaranteed by design, not tested.
A
= 25°C, V
DOUT
SCLK
DIN
DD
CS
= 3.3 V, tilt = 0°, unless otherwise noted.
Description
Fast mode, SMPL_TIME ≤ 0x07 (f
Normal mode, SMPL_TIME ≥ 0x08 (f
Chip select period, fast mode, SMPL_TIME ≤ 0x07 (f
Chip select period, normal mode, SMPL_TIME ≥ 0x08 (f
Chip select to clock edge
Data output valid after SCLK edge
Data input setup time before SCLK rising edge
Data input hold time after SCLK rising edge
Data output fall time
Data output rise time
CS high after SCLK edge
SCLK
CS
t
CS
1
MSB
W/R
2
(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)
DB14
t
DAV
t
DSU
3
s
A5
DB13
≥ 1024 Hz)
s
t
STALL
≤ 910 Hz)
Figure 2. SPI Chip Select Timing
4
t
DHD
=
t
DATA RATE
A4
t
Rev. A | Page 5 of 32
DB12
Figure 3. SPI Timing
DATA RATE
t
5
STALL
s
– 16/
A3
≥ 1024 Hz)
DB11
s
f
SCLK
≤ 910 Hz)
6
A2
DB10
Min
0.01
0.01
40
100
48.8
24.4
48.8
5
D2
DB2
1
15
D1
DB1
Typ
5
5
16
LSB
LSB
Max
2.5
1.0
100
12.5
12.5
t
SFS
ADIS16201
Unit
MHz
MHz
μs
μs
ns
ns
ns
ns
ns min
ns min
ns typ

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