SH3000 SEMTECH [Semtech Corporation], SH3000 Datasheet - Page 13

• Manufacturer Part Number: SH3000
• Description: Low-Power Programmable Multifunction Support IC for Microcontrollers
• Manufacturer: SEMTECH [Semtech Corporation]

Interrupt and Serial Interface
information between the SH3000 and the processor, and
as the interrupt line to the processor.
communicate using a single wire, bi-directional
asynchronous serial interface. The bit rate is
automatically determined by the SH3000. . At the
fastest possible rate, a read or write access of a single
byte from the register bank takes 5 µs.
located at 0x00–0x1F. Some of these registers are
accessed through a page operation. Pin 14, IO/Int, is
the serial communications interface and interrupt output
pin. This pin is internally weakly pulled to the opposite of
the programmed interrupt polarity. For example, if
interrupt is programmed to be active low, this pin is
weakly pulled to V
communicate with serial data streams. The host always
initiates communication. A data stream consists of the
following (in this order):
interrupt polarity) uses the middle bit to determine the bit
period of the serial data stream.
read, or 0,1,1 for a write. This protects against early
glitches hat might otherwise put the interface into an
invalid read or write access mode.
register.
which to change data direction. The value of a guard bit
does not matter.
The 8-bit data field is written to (read from) the register.
Copyright ©2003-2005 Semtech Corporation
SYSTEM MANAGEMENT
A single line is used to convey bi-directional
The polarity of the interrupt signal is programmable.
The SH3000 and the host microcontroller
The SH3000 contains 36 addressable registers
As shown in Figure 8, the SH3000 and the host
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•
•
•
•
•
Plus, for write streams only:
•
•
The 3-bit start field (1,0,1 or 0,1,0, depending on
The 3-bit read/write code consists of 1,1,0 for a
The 5-bit address field contains the address of the
A single guard bit gives the interface a safe period in
3-bit start field
3-bit read/write code
5-bit address field
1 guard bit
8-bit data field
2 parity bits
1 guard bit
2 acknowledge (ACK) bits
DD
when inactive.
13
Table 4: Minimum/Maximum Serial Bit Timing
Frequency
CLK
16 MHz
8 MHz
2 MHz
are an odd number of bits in the read/write, address and
data fields; the second parity bit is the inverse of the first.
the stream (to allow safe turnaround), and then two
acknowledge bits, which are a direct copy of the parity
bits, are driven back to the host to indicate a successful
write access.
access stream (read or write). The host can not start the
next access before receiving these bits.
the start bit field, and communication can take place
whenever CLKout is active, either at 32 kHz or at a
higher frequency. If the host microcontroller is running
synchronously to the CLKout generated by the SH3000
(which should generally be the case), then a minimum of
4 CLKout cycles per bit are required to maintain
communication integrity. If the host’s serial interface is
asynchronous to CLKout, then a minimum of 52 cycles
per bit are necessary. A maximum of 1024 CLKout
cycles per bit field is supported.
periods for the serial communications for CLKout
frequencies of 16 MHz, 8 MHz, and 2 MHz.
Interrupt Interface
14, IO/Int) also serves as the interrupt to the host
microcontroller. The polarity of the interrupt is software
programmable using the interrupt polarity bit (bit 6) of the
IPol_RCtune register (R0x11). This pin is asserted for
four cycles of CLKout, and then returns to the inactive
state.
Interrupt/Wake-up Timer to interrupt the host when it
reaches its end of count.
OUT
Two parity bits: The first parity bit is high when there
For write streams only, a guard bit is appended to
Two guard bits are appended to the end of the
The interface is self-timed based on the duration of
Table 4 displays the minimum and maximum bit
The serial communications line to the SH3000 (Pin
The interrupt line is used by the Periodic
synchronous
to
Minimum Bit
CLK
Period
250 ns
500 ns
(host
2 µs
OUT
SH3000 MicroBuddy™
)
asynchronous
Minimum Bit
to
V1.15
CLK
3.25 µs
Period
6.5 µs
(host
26 µs
OUT
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)
Maximum Bit
Period
128 µs
512 µs
64 µs