AM29DL400BB-120SF AMD [Advanced Micro Devices], AM29DL400BB-120SF Datasheet - Page 21

• Manufacturer Part Number: AM29DL400BB-120SF
• Description: 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

WRITE OPERATION STATUS
The device provides several bits to determine the
status of a write operation in the bank where a pro-
gram or erase operation is in progress: DQ2, DQ3,
DQ5, DQ6, DQ7, and RY/BY#. Table 6 and the fol-
lowing subsections describe the function of these
bits. DQ7, RY/BY#, and DQ6 each offer a method for
determining whether a program or erase operation is
complete or in progress. These three bits are dis-
cussed first.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host sys-
tem whether a n E mbed ded Prog ram or E rase
algorithm is in progress or completed, or whether a
bank is in Erase Suspend. Data# Polling is valid after
the rising edge of the final WE# pulse in the com-
mand sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Em-
bedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid sta-
tus information on DQ7. If a program address falls
within a protected sector, Data# Polling on DQ7 is
active for approximately 1 µs, then that bank returns
to reading array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the
Erase Suspend mode, Data# Polling produces a “1”
on DQ7. The system must provide an address within
any of the sectors selected for erasure to read valid
status information on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 µs,
then the bank returns to reading array data. If not all
selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ig-
nores the selected sectors that are protected.
However, if the system reads DQ7 at an address
within a protected sector, the status may not be
valid.
Just prior to the completion of an Embedded Pro-
g r a m o r E r a s e o p e r a t i o n , D Q 7 m a y c h a n g e
asynchronously with DQ0–DQ6 while Output Enable
(OE#) is asserted low. That is, the device may
change from providing status information to valid
data on DQ7. Depending on when the system sam-
ples the DQ7 output, it may read the status or valid
data. Even if the device has completed the program
or erase operation and DQ7 has valid data, the data
outputs on DQ0–DQ6 may be still invalid. Valid data
on DQ0–DQ7 will appear on successive read cycles.
Table 6 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm. Figure
Am29DL400B
20 in the AC Characteristics section shows the Data#
Polling timing diagram.
Notes:
1. VA = Valid address for programming. During a sector
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin
that indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid
after the rising edge of the final WE# pulse in the
command sequence. Since RY/BY# is an open-drain
output, several RY/BY# pins can be tied together in
parallel with a pull-up resistor to V
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a valid
address is any non-protected sector address.
may change simultaneously with DQ5.
No
Figure 5. Data# Polling Algorithm
Read DQ7–DQ0
Read DQ7–DQ0
DQ7 = Data?
DQ7 = Data?
Addr = VA
Addr = VA
DQ5 = 1?
START
FAIL
No
Yes
No
Yes
Yes
CC
.
PASS
19