AM29BL802CB-120RZE AMD [Advanced Micro Devices], AM29BL802CB-120RZE Datasheet - Page 12

• Manufacturer Part Number: AM29BL802CB-120RZE
• Description: 8 Megabit (512 K x 16-Bit) CMOS 3.0 Volt-only Burst Mode Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

IND# End of Burst Indicator
The IND# output signal goes low when the device is
ouputting the last word of a 32-word burst sequence
(word Da+31). When the starting address was loaded
with LBA#, the 5-bit burst address counter was set to
00000b. The counter increments to 11111b on the
32nd word in the burst sequence. If the system con-
tinues to assert BAA# low, on the next CLK the device
will output the starting address data (Da). The burst
address counter will be again set to 00000b, and will
have “wrapped around.”
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing sec-
tors of memory), the system must drive WE# and CE# to
V
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the Un-
lock Bypass mode, only two write cycles are required to
program a word, instead of four. The “Program Com-
mand Sequence” section has details on programming
data to the device using both standard and Unlock By-
pass command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select a
sector. The “Command Definitions” section has details
on erasing a sector or the entire chip, or suspending/re-
suming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The sys-
tem can then read autoselect codes from the internal
register (which is separate from the memory array) on
DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
I
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification ta-
bles and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
read specifications apply. Refer to “Write Operation Sta-
tus” for more information, and to “AC Characteristics” for
timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
10
CC2
IL
, and OE# to V
in the DC Characteristics table represents the ac-
IH
.
D A T A
Am29BL802C
CC
S H E E T
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range than
V
V
the standby current will be greater. The device requires
standard access time (t
vice is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the operation
is completed.
In the DC Characteristics table, I
the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for t
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I
Characteristics table represents the automatic sleep
mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system
drives the RESET# pin to V
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state machine
to reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept
another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the inter-
nal reset operation is complete, which requires a time of
t
thus monitor RY/BY# to determine whether the reset op-
eration is complete. If RESET# is asserted when a pro-
READY
IH
CC
.) If CE# and RESET# are held at V
IL
± 0.3 V, the device will be in the standby mode, but
but not within V
(during Embedded Algorithms). The system can
SS
CE
±0.3 V, the standby current will
22371C7 November 3, 2006
) for read access when the de-
IL
for at least a period of t
CC3
CC4
SS
). If RESET# is held
and I
±0.3 V, the device
IH
CC4
CC4
, but not within
CC
represents
in the DC
ACC
± 0.3 V.
+ 30
RP
,