AS7C331FT18A ALSC [Alliance Semiconductor Corporation], AS7C331FT18A Datasheet
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AS7C331FT18A
Related parts for AS7C331FT18A
AS7C331FT18A Summary of contents
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January 2005 3. Flow-through synchronous SRAM Features • Organization: 1,048,576 words x18 bits • Fast clock to data access: 6.8/7.5/8.5/10 ns • Fast OE access time: 3.5/4.0 ns • Fully synchronous flow-through operation • Asynchronous output enable ...
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Mb Synchronous SRAM products list Org Part Number 1MX18 AS7C331MPFS18A 512KX32 AS7C33512PFS32A 512KX36 AS7C33512PFS36A 1MX18 AS7C331MPFD18A 512KX32 AS7C33512PFD32A 512KX36 AS7C33512PFD36A 1MX18 AS7C331MFT18A 512KX32 AS7C33512FT32A 512KX36 AS7C33512FT36A 1MX18 AS7C331MNTD18A 512KX32 AS7C33512NTD32A 512KX36 AS7C33512NTD36A 1MX18 AS7C331MNTF18A 512KX32 AS7C33512NTF32A 512KX36 AS7C33512NTF36A 1 ...
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Pin assignments Pin configuration for 100-pin TQFP DDQ V 5 SSQ DQb0 8 DQb1 SSQ V 11 DDQ DQb2 12 DQb3 ...
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Functional description The AS7C331MFT18A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as 1,048,576 words x18 bits. Fast cycle times of 7.5/8.5/10/12 ns with clock access times (t easy memory expansion. Burst operation is initiated ...
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Signal descriptions Signal I/O Properties CLK I CLOCK Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock. A,A0,A1 I SYNC Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted. DQ[a,b] ...
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Write enable truth table (per byte) Function GWE L Write all bytes ( Write byte a H Write byte Read H Key don’t care low high; B WE, BWn ...
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Synchronous truth table 1 CE0 CE1 CE2 ADSP ADSC ...
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Absolute maximum ratings Parameter Power supply voltage relative to GND Input voltage relative to GND (input pins) Input voltage relative to GND (I/O pins) Power dissipation DC output current Storage temperature Temperature under bias Note: Stresses greater than those listed ...
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DC electrical characteristics for 3.3V I/O operation Parameter Sym † Input leakage current |I Output leakage current |I Input high (logic 1) voltage V Input low (logic 0) voltage V Output high voltage V Output low voltage V DC electrical ...
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Timing characteristics over operating range Parameter Cycle time Clock access time Output enable low to data valid Clock high to output low Z Data output invalid from clock high Output enable low to output low Z Output enable high to ...
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Key to switching waveforms Rising input Timing waveform of read cycle CLK t t ADSPS ADSPH ADSP t ADSCS ADSC Address GWE, BWE t t CSS CSH CE0, CE2 CE1 ...
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Timing waveform of write cycle t CH CLK t ADSPS t ADSPH ADSP ADSC Address BWE BW[a:b] t CSS t CSH CE0, CE2 CE1 ADV OE Din D(A1) Read Suspend Q(A1) D(A1) Note: Ý = ...
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Timing waveform of read/write cycle (ADSP Controlled; ADSC High) CLK t ADSPS t ADSPH ADSP Address A1 BWE BW[a:b] CE0, CE2 CE1 ADV OE Din LZC Dout Q(A1) Read Q(A1) Note: Ý = XOR when LBO = ...
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Timing waveform of read/write cycle(ADSC controlled, ADSP = HIGH) CLK t t ADSCS ADSCH ADSC ADDRESS BWE BW[a: CSS CSH CE0,CE2 CE1 LZOE Q(A1) Q(A2) Dout Din READ READ Q(A1) Q(A2) ...
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Timing waveform of power down cycle CLK t t ADSPS ADSPS ADSP ADSC A1 ADDRESS BWE BW[a: CSS CSH CE0,CE2 CE1 ADV LZOE Din Dout Q(A1) t PDS ZZ ZZ Setup Cycle t ZZI ...
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AC test conditions • Output load: For LZC LZOE HZOE • Input pulse level: GND to 3V. See Figure A. • Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure ...
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Package dimensions 100-pin TQFP (quad flat pack) TQFP Min Max c A1 0.05 0.15 A2 1.35 1. 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.85 16.15 He 21.80 22.20 ...
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Ordering information Package Width –68 & AS7C331MFT18A-68TQC TQFP x18 AS7C331MFT18A-68TQI Note: Add suffix ‘N’ to the above part numbers for Lead Free Parts (Ex. AS7C331MFT18A-85TQCN) Part numbering guide AS7C Alliance Semiconductor SRAM prefix 2. ...
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