K7D801871B-HC30 Samsung semiconductor, K7D801871B-HC30 Datasheet - Page 5

• Manufacturer Part Number: K7D801871B-HC30
• Description: 256Kx36 & 512Kx18 SRAM
• Manufacturer: Samsung semiconductor

K7D803671B
K7D801871B
BURST SEQUENCE TABLE
TRUTH TABLE
NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care".
4 Burst Operation for Interleaved Burst (LBO = V
NOTE : - For Interleave Burst LBO = V
4 Burst Operation for Linear Burst (LBO = V
Linear Burst Mode
Interleaved Burst
K
L
Fourth Address
Fourth Address
- K & K are complementary.
First Address
First Address
G
X
X
X
X
X
L
L
B1
X
H
H
L
L
L
L
A
A
0
0
1
1
0
0
1
1
DDQ
1
1
Case 1
Case 1
is recommended. If LBO = V
B2
X
H
H
H
L
L
L
A
A
0
1
0
1
0
1
0
1
0
0
SS
)
B3
H
H
X
X
L
L
X
DDQ
A
A
0
0
1
1
0
1
1
0
1
1
DD
Case 2
)
Case 2
- 5 -
, it must not exceed 2.63V.
DOUT
DOUT
Hi-Z
Hi-Z
DIN
DIN
DQ
B
A
A
1
0
1
0
1
0
1
0
0
0
256Kx36 & 512Kx18 SRAM
A
A
1
1
0
0
1
1
0
0
1
1
Case 3
Case 3
No Operation, Pipeline High-Z
Increment Address, Continue
Load Address, Double Read
Load Address, Double Write
Load Address, Single Read
Load Address, Single Write
A
A
0
1
0
1
0
1
0
1
0
0
Clock Stop
Operation
A
A
1
1
0
0
1
0
0
1
1
1
Case 4
Case 4
January. 2002
A
A
Rev 4.0
1
0
1
0
1
0
1
0
0
0