K7A801809B Samsung semiconductor, K7A801809B Datasheet - Page 9

• Manufacturer Part Number: K7A801809B
• Description: 256Kx36 & 512Kx18-Bit Synchronous Pipelined Burst SRAM
• Manufacturer: Samsung semiconductor

K7A803601M
K7A801801M
Dout
AC TIMING CHARACTERISTICS
Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
Cycle Time
Clock Access Time
Output Enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to Output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
Address Status Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High (GW, BW, WE
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
Address Status Hold from Clock High
Data Hold from Clock High
Write Hold from Clock High (GW, BW, WE
Address Advance Hold from Clock High
Chip Select Hold from Clock High
ZZ High to Power Down
ZZ Low to Power Up
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
4. At any given voltage and temperature, t
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
Output Load(A)
PARAMETER
Zo=50
X
)
X
RL=50
HZC
)
30pF*
(V
* Including Scope and Jig Capacitance
is less than t
DD
=3.3V+0.165V/-0.165V, T
SYMBOL
VL=1.5V for 3.3V I/O
256Kx36 & 512Kx18 Synchronous SRAM
t
t
t
t
t
HZOE
t
t
ADVH
t
t
t
t
LZOE
ADVS
t
t
t
t
t
t
t
CYC
HZC
t
t
t
t
CSS
t
t
CSH
PDS
PUS
LZC
LZC
WS
WH
CD
OE
OH
CH
AS
SS
DS
AH
SH
DH
CL
V
DDQ
Fig. 1
- 9 -
/2 for 2.5V I/O
MIN
7.2
1.5
1.5
2.5
2.5
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
0
0
2
2
-
-
-
-14
MAX
4.0
4.0
3.5
3.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
A
=0 C to +70 C)
353
Output Load(B),
(for t
Dout
MIN
8.5
1.5
1.5
2.5
2.5
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
0
0
2
2
-
-
-
LZC
1538
-11
, t
LZOE
MAX
4.2
4.2
3.5
3.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
, t
HZOE
MIN
& t
1.5
1.5
3.0
3.0
2.0
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
10
0
0
2
2
-
-
-
HZC
-10
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
319
5pF*
)
MAX
4.5
4.5
4.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1667
May 1999
Rev 3.0
UNIT
cycle
cycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns