M3488 ST Microelectronics, M3488 Datasheet - Page 9

• Manufacturer Part Number: M3488
• Description: 256 x 256 DIGITAL SWITCHING MATRIX
• Manufacturer: ST Microelectronics

READ OPERATION TIMING
GENERAL DESCRIPTION
The M3488 is intendedfor large telephoneswitching
systems, mainly central exchanges, digital line con-
centrators and private branch exchanges where a
distributed microcomputer control approach is ex-
tensively used. It consists of a speech memory
(SM), a control memory (CM), a serial/parallel and
a parallel/serial converter, an internal parallel bus,
an interface (8 data lines, 11 control signals) and
dedicated control logic.
By means of repeated clock division two timebases
are generated. These are preset from an external
synchronization signal to two specific count num-
bers so that sequential scanning of the bases give
synchronous addresses to the memories and I/O
channel controls. Different preset count numbers
are needed because of processing delays and
data path direction. The timebase for the input chan-
nels is delayed and the timebase for output chan-
nels is advanced with respect to the actual time.
Each serial PCM input channel is converted to par-
allel data and stored in the speech memory at the
beginning of any new time slot (according to first
timebase) in the location determined by input pin
number and time slot number. The control memory
CM maintains the correspondencesbetween input
and output channels. More exactly, for any output
pin/outputchannel combination the control memory
gives either the full address of the speech memory
location involved in the PCM transfer or an 8-bit
word to be supplied to the parallel/serial output con-
verter. A 9
source for output links, low for SM, high for CM.
The late timebase is used to scan the output chan-
nels and to determine the pins to be serviced within
each channel ; enough idle cycles are left to the mi-
croprocessor for asynchronousinstruction process-
ing.
Two 8-bit registers OR1 and OR2 supply feedback
data for control or diagnosticpurposes ; OR1 comes
from internal bus i.e. from memories, OR2 gives an
opcode copy and additional data to the microcom-
puter. A four byte-five bit stack register and an in-
struction register, under microcomputer control,
store input data available at the interface.
Dedicated logic, under controlof the microprocessor
interface, extracts the 0 channel content of any se-
lected PCM input bus, using spare cycles of SM.
th
bit at each CM location defines the data
M3488
9/18