K6X4016C3F-B Samsung semiconductor, K6X4016C3F-B Datasheet
K6X4016C3F-B
Related parts for K6X4016C3F-B
K6X4016C3F-B Summary of contents
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... K6X4016C3F Family Document Title 256Kx16 bit Low Power full CMOS Static RAM Revision History Revision No. History 0.0 Initial draft 0.1 Revised Added Commercial Product. Deleted 44-TSOP2-400R Package Type. 1.0 Finalized - Changed I from 10mA to 5mA CC - Changed I 1 from 10mA to 7mA CC - Changed I 2 from 50mA to 30mA ...
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... Organization: 256Kx16 Power Supply Voltage: 4.5~5.5V Low Data Retention Voltage: 2V(Min) Three state output and TTL compatible Package Type: 44-TSOP2-400F PRODUCT FAMILY Product Family Operating Temperature Vcc Range Commercial( C) K6X4016C3F-B 0~70 C) K6X4016C3F-F Industrial (-40~85 K6X4016C3F-Q C) Automotive (-40~125 1. The parameter is measured with 50pF test load. ...
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... Power Deselected Standby Output Disabled Active Output Disabled Active Lower Byte Read Active Upper Byte Read Active Word Read Active Lower Byte Write Active Upper Byte Write Active Word Write Active Unit Remark K6X4016C3F-B C K6X4016C3F-F K6X4016C3F-Q Revision 1.0 September 2003 ...
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... Other inputs = Vcc-0.2V, Other inputs=0~Vcc 4 CMOS SRAM Typ Max Unit 5.0 5 Vcc+0 0.8 V Min Max Unit - Min Typ Max Unit - IL 0.4 2 0.4 K6X4016C3F K6X4016C3F K6X4016C3F Revision 1.0 September 2003 ...
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... WHZ Test Condition CS Vcc-0.2V K6X4016C3F-B Vcc=3.0V, CS Vcc-0.2V K6X4016C3F-F K6X4016C3F-Q See data retention waveform 5 CMOS SRAM -40 to 125 Speed Bins Units 70ns Min Max - ...
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... K6X4016C3F Family TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address Data Out Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) Address CS UB Data out High-Z NOTES (READ CYCLE and are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage ...
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... K6X4016C3F Family TIMING WAVEFORM OF WRITE CYCLE(1) Address CS UB Data in Data Undefined Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address CS UB Data in Data out (WE Controlled CW( WP(1) t AS(3) t High-Z t WHZ (CS Controlled AS(3) CW( WP( High-Z 7 CMOS SRAM ...
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... K6X4016C3F Family TIMING WAVEFORM OF WRITE CYCLE(3) Address CS UB Data in Data out NOTES (WRITE CYCLE wri e occurs during the overlap for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transi- tion when CS goes high and WE goes high. The t 2 ...
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... K6X4016C3F Family PACKAGE DIMENSIONS 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) #44 #1 18.81 MAX. 0.741 18.41 0.10 0.725 0.004 0.35 0.805 0. 0.032 0.014 0.004 #23 11.76 0.20 0.463 0.008 #22 1.00 0.10 0.039 0.004 1.20 MAX. 0.047 0.10 MAX 0.004 0.80 0.0315 9 CMOS SRAM Units: millimeter(inch) 0~8 0. 0.010 0.45 ~0.75 0.018 ~ 0.030 0. 0.020 Revision 1.0 September 2003 ...