W49V002 Winbond, W49V002 Datasheet - Page 25

• Manufacturer Part Number: W49V002
• Description: 256K X 8 CMOS FLASH MEMORY WITH FWH INTERFACE
• Manufacturer: Winbond

Timing Waveforms for LPC Interface Mode, continued
Toggle Bit Timing Diagram
LAD[3:0]
LAD[3:0]
#RESET
#LFRAM
LAD[3:0]
All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000.
#LFRAM
#RESET
#RESET
#LFRAM
CLK
CLK
CLK
1 Clock
1 Clock
1st Start
1 Clock
0000b
0000b
Start
0000b
Start
1 Clock
1 Clock
1 Clock
Memory
Write
Cycle
011Xb
Memory
Read
Cycle
010Xb
Memory
Read
Cycle
010Xb
A[31:28]
A[31:28]
A[31:28]
A[27:24]
A[27:24]
A[27:24]
Write the last command(program or erase) to the device in LPC mode.
A[23:20]
A[23:20]
A[23:20]
Load Address "An" in 8 Clocks
Read the DQ6 to see if the internal write complete or not.
Load Address in 8 Clocks
Load Address in 8 Clocks
When internal write complete, the DQ6 will stop toggle.
A[19:16]
A[19:16]
A[19:16]
Address
Address
Address
A[15:12]
XXXXb
XXXXb
XXXXb
XXXXb
A[11:8]
- 25 -
XXXXb
XXXXb
A[7:4]
XXXXb
XXXXb
A[3:0]
Preliminary W49V002A
D[3:0]
Load Data "Dn"
1111b
in 2 Clocks
1111b
2 Clocks
2 Clocks
Data
TAR
TAR
Publication Release Date: April 2001
D[7:4]
Tri-State
Tri-State 0000b
1 Clock
1 Clock
1111b
0000b
Sync
Sync
2 Clocks
TAR
Tri-State
Data out 2 Clocks
Data out 2 Clocks
XXXXb
XXXXb
Data
Data
1 Clock
X,D6,XXb
X,D6,XXb
0000b
Sync
TAR
TAR
TAR
Revision A1
Start next
command
1 Clock
1 Clock
1 Clock
Next Start
Next Start
0000b
0000b