PSD913F1-B-90JI ST Microelectronics, PSD913F1-B-90JI Datasheet - Page 46

• Manufacturer Part Number: PSD913F1-B-90JI
• Description: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
• Manufacturer: ST Microelectronics

The
PSD9XX
Functional
Blocks
(cont.)
42
PSD9XX Family
9.4 I/O Ports
There are four programmable I/O ports: Ports A, B, C, and D. Each of the ports is eight
bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus
allowing multiple functions per port. The ports are configured using PSDsoft or by the
microcontroller writing to on-chip registers in the CSIOP address space.
The topics discussed in this section are:
9.4.1 General Port Architecture
The general architecture of the I/O Port is shown in Figure 19. Individual Port architectures
are shown in Figures 20 through 22. In general, once the purpose for a port pin has been
defined, that pin will no longer be available for other purposes. Exceptions will be noted.
As shown in Figure 19, the ports contain an output multiplexer whose selects are driven
by the configuration bits in the Control Registers (Ports A and B only) and PSDsoft. Inputs
to the multiplexer include the following:
The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be
read. The PDB is connected to the Internal Data Bus for feedback and can be read by the
microcontroller. The Data Out, Direction and Control Registers, and port pin input are all
connected to the PDB.
The contents of these registers can be altered by the microcontroller. The PDB feedback
path allows the microcontroller to check the contents of the registers.
•
•
•
•
•
Output data from the Data Out Register
Latched address outputs
General Purpose PLD (GPLD) outputs (external chip selects)
General Port Architecture
Port Operating Modes
Port Configuration Registers
Port Data Registers
Individual Port Functionality.
Preliminary Information