SAA5500PS Philips Semiconductors, SAA5500PS Datasheet - Page 31

• Manufacturer Part Number: SAA5500PS
• Description: Standard TV Microcontrollers with On-Screen Display(OSD)
• Manufacturer: Philips Semiconductors

Philips Semiconductors
10 REDUCED POWER MODES
There are two power saving modes, Idle and Power-down,
incorporated into the 10 page devices. There is an
additional Standby mode incorporated into the 1 page
devices. When utilizing any mode, power to the device
(V
saving is achieved by clock gating on a section by section
basis.
10.1
During Idle mode, Acquisition, Display and the Central
Processing Unit (CPU) sections of the device are disabled.
The following functions remain active:
To enter Idle mode the IDL bit in the PCON register must
be set. The Watchdog Timer must be disabled prior to
entering the Idle mode to prevent the device being reset.
Once in Idle mode, the crystal oscillator continues to run,
but the internal clock to the CPU, Acquisition and Display
are gated out. However, the clocks to the Memory
interface, I
Timer and Pulse Width Modulators are maintained.
The CPU state is frozen along with the status of all SFRs,
internal RAM contents are maintained, as are the device
output pin values.
Since the output values on Red Green Blue (RGB) and the
Video Data Switch (VDS) are maintained the display
output must be disabled before entering this mode.
There are three methods to recover from Idle mode:
1999 Oct 27
DDP
Memory interface
I
Timer/Counters
Watchdog Timer
Pulse Width Modulators.
Assertion of an enabled interrupt will cause the IDL bit to
be cleared by hardware, thus terminating Idle mode.
The interrupt is serviced, and following the instruction
RETI, the next instruction to be executed will be the one
after the instruction that put the device into Idle mode.
A second method of exiting the Idle mode is via an
interrupt generated by the SAD DC Compare circuit.
When the device is configured in this mode, detection of
an analog threshold at the input to the SAD may be used
to trigger wake-up of the device i.e. TV Front Panel
Key-press. As above, the interrupt is serviced, and
following the instruction RETI, the next instruction to be
executed will be the one following the instruction that put
the device into Idle mode.
Standard TV microcontrollers with
On-Screen Display (OSD)
2
C-bus interface
, V
Idle mode
DDC
2
C-bus interface, Timer/Counters, Watchdog
and V
DDA
) should be maintained, since power
31
10.2
In Power-down mode the crystal oscillator is stopped.
The contents of all SFRs and Data memory are
maintained, However, the contents of the Auxiliary/Display
memory are lost. The port pins maintain the values defined
by their associated SFRs. Since the output values on RGB
and VDS are maintained the display output must be made
inactive before entering Power-down mode.
The Power-down mode is activated by setting the PD bit in
the PCON register. It is advised to disable the Watchdog
Timer prior to entering power-down.
There are three methods of exiting power-down:
The third method of terminating Idle mode is with an
external hardware reset. Since the oscillator is running,
the hardware reset need only be active for two machine
cycles (24 clocks at 12 MHz) to complete the reset
operation. Reset defines all SFRs and Display memory
to an initialized state, but maintains all other RAM
values. Code execution commences with the Program
Counter set to ‘0000’.
An external interrupt provides the first mechanism for
waking from power-down. Since the clock is stopped,
external interrupts needs to be set level sensitive prior to
entering power-down. The interrupt is serviced, and
following the instruction RETI, the next instruction to be
executed will be the one after the instruction that put the
device into Power-down mode.
A second method of exiting power-down is via an
interrupt generated by the SAD DC Compare circuit.
When the device is configured in this mode, detection of
a certain analog threshold at the input to the SAD may
be used to trigger wake-up of the device i.e. TV Front
Panel Key-press. As above, the interrupt is serviced,
and following the instruction RETI, the next instruction to
be executed will be the one following the instruction that
put the device into power-down.
The third method of terminating the Power-down mode
is with an external hardware reset. Reset defines all
SFRs and Display memory, but maintains all other RAM
values. Code execution commences with the Program
Counter set to ‘0000’.
Power-down mode
Preliminary specification
SAA55xx