SAA5281GP Philips Semiconductors, SAA5281GP Datasheet - Page 22

• Manufacturer Part Number: SAA5281GP
• Description: Integrated Video input processor and Teletext decoder IVT1.8
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Notes to Table 7
1. The dash ( ) indicates these bits are inactive and must be written to logic 0 for future compatibility.
2. Certain registers are auto-incremented following an I
3. All bits in Registers R0 to R13 are cleared to logic 0 on power-up except bits D0 and D1 of Registers R1, R5 and R6
4. All memory is cleared to space (00100000) on power-up, except Row 0 Column 7 Chapter 0, which is alpha white
Table 8 Register description
1996 Nov 04
R0 AVANCED CONTROL - auto-increments to Register 1
R11/R11B SELECT
VCR MODE
DISABLE ODD/EVEN
CBB SLAVE SYNC
DISABLE HDR ROLL
AUTO ODD/EVEN
FREE RUN PLL
X/24 POS
R1 MODE - auto-increments to Register 2
T0, T1
TCS ON
DEW/FULL FIELD
EXT PKT ENABLE
ACQ ON/OFF
7 + P/8-BIT
VCS TO SCS
R2 PAGE REQUEST ADDRESS - auto-increments to Register 3
SC0 to SC2
0
ACQ CCT A0, A1
BANK SELECT A2
HAM CHECK 27, 8/30
R3 PAGE REQUEST DATA - does not auto-increment
PRD0 to PRD4
Integrated Video input processor and
Teletext decoder (IVT1.8*)
R4 to R7 and R8 to R12 or R13.
which are set to logic 1.
(00000111) as the acquisition circuit is enabled but all pages are on hold.
REGISTER BIT D0 TO D7
Selects reading of R11 if LOW or R11B if HIGH.
If logic 1 selects short time constant mode of PLL.
Forces ODD/EVEN output LOW when logic 1 (see Table 9).
When set will modify internal slave sync timing to allow connection to sandcastle of
Philips one-chip TV IC (TDA8362).
Stops the display update of rolling time and green rolling header during page
requests when logic 1. Time updates on page reception only.
If logic 1 then ODD/EVEN output only active when no TV picture displayed
(see Table 9).
Will force the display PLL to free run at 6 MHz when logic 1.
Automatic display of FASTEXT prompt row when logic 1. Will also cause Row 24
data transmitted by packet 26 to be written to display, rather than extension
memory.
Interlace/non-interlace 312/313 line control (see Table 10).
Text composite sync or direct sync select (see Table 10 for FFB mode selection).
Field-flyback or full-channel mode.
Enables reception and storage of extension packets when logic 1.
Acquisition circuits turned off when logic 1.
7 bits with parity checking or 8-bit mode.
Connects VCS from video sync separator to display field sync detector to enable
stable display of 60 Hz status messages when logic 1.
Start column for page request data (see Table 11).
Must be logic 0 for normal operation.
Selects one of four acquisition circuits.
Selects bank of four pages being addressed for acquisition.
8/4 Hamming check packet 27 and 8/30 data.
See Table 11.
2
C-bus transmission byte. These are Register R0 to R3,
22
FUNCTION
Preliminary specification
SAA5281