GS8320Z18T ETC, GS8320Z18T Datasheet - Page 9

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GS8320Z18T

Manufacturer Part Number
GS8320Z18T
Description
(GS8320Z18T/36T) 36Mb Pipelined and Flow Through Synchronous NBT SRAM
Manufacturer
ETC
Datasheet
Rev: 1.01 10/2001
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Pipeline Mode Data I/O State Diagram
Key
Current State (n)
Clock (CK)
Command
Intermediate
ƒ
Current State and Next State Definition for
Transition
Input Command Code
Intermediate State (N+1)
High Z
(Data In)
B W
Current State
n
D
R
Transition
ƒ
Intermediate
Next State (n+2)
9/25
n+1
B
Intermediate
Intermediate
Intermediate
D
W
State
High Z
ƒ
R
Pipeline Mode Data I/O State Diagram
Intermediate
Notes:
1. The Hold command (CKE Low) is not
2. W, R, B, and D represent input command
GS8320Z18/36T-250/225/200/166/150/133
codes as indicated in the Truth Tables.
shown because it prevents any state change.
n+2
Next State
W
ƒ
D
Data Out
(Q Valid)
R
n+3
B
© 2001, Giga Semiconductor, Inc.
Intermediate
ƒ
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