GS88018AT-133 ETC, GS88018AT-133 Datasheet - Page 5

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GS88018AT-133

Manufacturer Part Number
GS88018AT-133
Description
512K x 18/ 256K x 32/ 256K x 36 9Mb Sync Burst SRAMs
Manufacturer
ETC
Datasheet
TQFP Pin Description
Rev: 1.02 9/2002
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
B
ADSP, ADSC
DQ
DQ
DQ
DQ
A
Symbol
, B
A
A
E
A1
B1
C1
D1
V
ADV
LBO
2
V
GW
V
BW
0
A
NC
B,
CK
1
ZZ
–A
E
FT
DDQ
G
–DQ
–DQ
–DQ
–DQ
, A
, E
DD
SS
18
B
2
17
C
1
3
, B
A9
B9
C9
D9
D
Type
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
5/26
Address Strobe (Processor, Cache Controller); active low
Address field LSBs and Address Counter preset Inputs
Byte Write Enable for DQ
Burst address counter advance enable; active low
Global Write Enable—Writes all bytes; active low
Byte Write—Writes all enabled bytes; active low
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Sleep Mode control; active high
Clock Input Signal; active high
Output driver power supply
Data Input and Output pin
Output Enable; active low
GS88018/32/36AT-250/225/200/166/150/133
Chip Enable; active high
Chip Enable; active low
I/O and Core Ground
Core power supply
Address Inputs
Description
Address Input
No Connect
A
, DQ
B
Data I/Os; active low
© 2001, Giga Semiconductor, Inc.

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