K9F1208D0B Samsung semiconductor, K9F1208D0B Datasheet - Page 42
K9F1208D0B
Manufacturer Part Number
K9F1208D0B
Description
64M x 8 Bit NAND Flash Memory
Manufacturer
Samsung semiconductor
Datasheet
1.K9F1208D0B.pdf
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K9F1208R0B
K9F1208B0B
K9F1208U0B
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is
already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST
after the Reset command is written. Refer to Figure 22 below.
Figure 22. RESET Operation
Table5. Device Status
R/B
I/O
0
~
7
Operation Mode
FFh
After Power-up
Read 1
t
RST
42
Waiting for next command
After Reset
FLASH MEMORY
Preliminary
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