SAA4992 Philips, SAA4992 Datasheet - Page 13
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SAA4992
Manufacturer Part Number
SAA4992
Description
Field and line rate converter with noise reduction
Manufacturer
Philips
Datasheet
1.SAA4992.pdf
(20 pages)
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Quantity
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Part Number:
SAA4992H
Manufacturer:
NXPLIPS
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Philips Semiconductors
Register 01: Interrupt (reset state X00X XXXX)
Register R01 is WRITE only.
Table 9 Register 01.
Table 10 Register 01 bit description.
Register 02 to 0F (HEX): VPS data bytes
A single VPS data bytes is stored as two memory bytes, the least significant nibble of both memory bytes is the data
making up the single VPS data byte. The most significant nibble of each memory byte is used to indicate a biphase error
in the least significant nibble. This is indicated by the least significant bit being set, the top three bits are not used and
are fixed to logic 0 (see Table 11).
Table 11 VPS data bytes.
Note
1. Equivalent to VPS B5 0101 1100 (MSB to LSB).
Table 12 Register 02.
Register 11 to 1D (HEX): Teletext packet 8/30/2 data bytes
Data is stored as single bytes. The four least significant bits represent the data. The fifth bit if set indicates a Hamming
error in the stored data. The top three bits of the byte are not used and are fixed to logic 0.
Table 13 Register 11.
June 1994
8/30/2 IE
VPS IE
Dual standard PDC decoder
SYMBOL
D7
D7
D7
ADDRESS (HEX)
8/30/2 IE
02
03
BIT
D6
D6
D6
D6
D5
8/30/2 Interrupt Enable.
This allows the reception of Teletext packet 8/30/2 data to be signalled on the INT pin.
When logic 0 reception of Teletext packet 8/30/2 data is not signalled on INT pin.
When logic 1 reception of Teletext packet 8/30/2 data is signalled on INT pin.
VPS Interrupt Enable.
This allows the reception of VPS data to be signalled on the INT pin.
When logic 0 reception of VPS data is not signalled on INT pin.
When logic 1 reception of VPS data is signalled on INT pin.
VPS IE
D5
D5
D5
VPS B5 least significant nibble
VPS B5 most significant nibble
ERROR BIT
ERROR BIT
HAMMING
BIPHASE
D4
D4
D4
REGISTER
13
DATA BIT 3
DATA BIT 3
D3
D3
D3
FUNCTION
DATA BIT 2 DATA BIT 1
DATA BIT 2 DATA BIT 1
D2
D2
D2
0000 0101
0000 1100
D1
D1
D1
DATA
Objective specification
SAA5233
(1)
(1)
DATA BIT 0
DATA BIT 0
D0
D0
D0