K4T51043Q Samsung, K4T51043Q Datasheet - Page 19

• Manufacturer Part Number: K4T51043Q
• Description: 512Mb B-die DDR2 SDRAM
• Manufacturer: Samsung

512Mb B-die DDR2 SDRAM
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
DQ output access time from
CK/CK
DQS output access time
from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input hold time
DQ and DM input setup
time
Control & Address input
pulse width for each input
DQ and DM input pulse
width for each input
Data-out high-impedance
time from CK/CK
DQS low-impedance time
from CK/CK
DQ low-impedance time
from CK/CK
DQS-DQ skew for DQS and
associated DQ signals
DQ hold skew factor
DQ/DQS output hold time
from DQS
First DQS latching
transition to associated
clock edge
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK
setup time
DQS falling edge hold time
from CK
Mode register set command
cycle time
Write postamble
Parameter
Symbol
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDH(base)
tDS(base)
tIPW
tDIPW
tHZ
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
2* tACmi
min(tCL,
tAC min
tQHS
3750
tHP -
-0.25
min
tCH)
0.45
0.45
0.35
0.35
-500
-450
225
100
0.35
0.6
0.2
0.2
0.4
n
2
x
x
x
DDR2-533
max
+500
+450
8000
0.55
0.55
0.25
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max
max
max
tAC
tAC
tAC
300
400
0.6
x
x
x
x
x
x
x
x
x
x
x
2* tACmi
min(tCL,
tAC min
tQHS
tHP -
-0.25
5000
min
-600
-500
0.45
0.45
tCH)
0.35
0.35
0.35
275
150
0.6
0.2
0.2
0.4
x
n
2
x
x
DDR2-400
tAC max
tAC max
tAC max
max
+600
+500
8000
0.55
0.55
0.25
350
450
0.6
x
x
x
x
x
x
x
x
x
x
x
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Notes
15,16,17
15,16,17
20,21
,20
,21
24
27
27
22
21
19
Rev. 1.4 Feb. 2005
DDR2 SDRAM