ZL50234GD ETC, ZL50234GD Datasheet - Page 12
![no-image](/images/no-image-200.jpg)
ZL50234GD
Manufacturer Part Number
ZL50234GD
Description
8 Channel Voice Echo Canceller
Manufacturer
ETC
Datasheet
1.ZL50234GD.pdf
(41 pages)
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12
2.1
In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in
Figure 6, providing 64 milliseconds of echo cancellation in two channels simultaneously.
2.2
In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming
from both directions in a single channel providing full-duplex 64ms echo cancellation. See Figure 7. This
configuration uses only one timeslot on PORT1 and PORT2 and the second timeslot normally associated with ECB
contains zero code. Back-to-Back configuration allows a no-glue interface for applications where bidirectional echo
cancellation is required.
Back-to-Back configuration is selected by writing a “1” into the BBM bit of Control Register 1 for both Echo Canceller
A and Echo Canceller B for a given group of echo canceller. Table 4 shows the 4 groups of 2 cancellers that can be
configured into Back-to-Back.
ZL50234
Normal Configuration
Back-to-Back Configuration
PORT2
echo
path B
Figure 7 - Back-to-Back Device Configuration (64ms)
Rout
echo
path A
Sin
PORT2
Figure 6 - Normal Device Configuration (64ms)
Rout
echo
path
Sin
ECA
Filter (64ms)
channel B
channel A
channel B
channel A
Adaptive
ECA
ECB
-
Zarlink Semiconductor Inc.
+
Filter (64ms)
Filter (64ms)
Adaptive
Adaptive
-
-
+
+
Filter (64ms)
Adaptive
ECB
+
-
echo
path
PORT1
Sout
Rin
PORT1
Sout
Rin
Data Sheet
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