ZL50120 Zarlink, ZL50120 Datasheet - Page 80

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ZL50120

Manufacturer Part Number
ZL50120
Description
32 / 64 / 128 Channel CESoP Processors
Manufacturer
Zarlink
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ZL50120GAG2
Manufacturer:
st
Quantity:
7
12.6.5
GTXCLK period
GTXCLK high wide time
GTXCLK low wide time
TXD[9:0] Output Delay
(GTXCLK rising edge)
RCB0/RBC1 period
RCB0/RBC1 high wide time
RCB0/RBC1 low wide time
RCB0/RBC1 rise time
RCB0/RBC1 fall time
RXD[9:0] setup time (RCB0
rising edge)
RXD[9:0] hold time (RCB0
rising edge)
REFCLK period
REFCLK high wide time
REFCLK low wide time
Signal_Detect
TBI Interface Timing
Parameter
GTXCLK
TXD[9:0]
/I/
/S/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /T/ /R/ /I/
t
GC
Symbol
Figure 36 - TBI Transmit Timing Diagram
t
t
t
t
t
t
t
t
t
t
t
t
t
t
GC
GH
GL
DV
RC
RH
RR
RF
DS
DH
FC
FH
Table 34 - TBI Timing - 1000 Mbps
RL
FL
ZL50115/16/17/18/19/20
Zarlink Semiconductor Inc.
t
DV
Min.
7.5
2.5
2.5
7.5
2.5
2.5
15
1
5
5
2
1
-
-
80
1000 Mbps
Typ.
16
-
-
-
-
-
-
-
-
-
-
-
-
-
Max.
8.5
8.5
17
6
2
2
-
-
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Load = 25 pF
Data Sheet
Notes

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