SN54-74LS390 ON Semiconductor, SN54-74LS390 Datasheet - Page 2

• Manufacturer Part Number: SN54-74LS390
• Description: DUAL DECADE COUNTER; DUAL 4-STAGE BINARY COUNTER
• Manufacturer: ON Semiconductor

FUNCTIONAL DESCRIPTION
binary sequence, as indicated in the 16 Truth Table. The first
flip-flop is triggered by HIGH-to-LOW transitions of the CP
input signal. Each of the other flip-flops is triggered by a
HIGH-to-LOW transition of the Q output of the preceding
flip-flop. Thus state changes of the Q outputs do not occur
simultaneously. This means that logic signals derived from
combinations of these outputs will be subject to decoding
spikes and, therefore, should not be used as clocks for other
counters, registers or flip-flops. A HIGH signal on MR forces
all outputs to the LOW state and prevents counting.
independent except for the common MR function. The
Each half of the SN54 / 74LS393 operates in the Modulo 16
Each half of the LS390 contains a
MR
CP
MR
CP 1
CP 0
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b)
PIN NAMES
CP
CP 0
CP 1
MR
Q 0 – Q 3
C D
Temperature Ranges.
C D
K CP
K CP
SN54 / 74LS393 LOGIC DIAGRAM (one half shown)
SN54/74LS390 SN54/74LS393
SN54 / 74LS390 LOGIC DIAGRAM (one half shown)
Q
J
Clock (Active LOW going edge)
Input to +16 (LS393)
Clock (Active LOW going edge)
Input to 2 (LS390)
Clock (Active LOW going edge)
Input to 5 (LS390)
Master Reset (Active HIGH) Input
Flip-Flop outputs (Note b)
J
Q
Q 0
Q 0
5 section that is
FAST AND LS TTL DATA
C D
C D
K CP
K CP
5
5-2
Q
J
J
Q
Q 1
Q 1
section operates in 4.2.1 binary sequence, as shown in the 5
Truth Table, with the third stage output exhibiting a 20% duty
cycle when the input frequency is constant. To obtain a 10
function having a 50% duty cycle output, connect the input
signal to CP 1 and connect the Q 3 output to the CP 0 input; the
Q 0 output provides the desired 50% duty cycle output. If the
input frequency is connected to CP 0 and the Q 0 output is
connected to CP 1 , a decade divider operating in the 8.4.2.1
BCD code is obtained, as shown in the BCD Truth Table. Since
the flip-flops change state asynchronously, logic signals
derived from combinations of LS390 outputs are also subject
to decoding spikes. A HIGH signal on MR forces all outputs
LOW and prevents counting.
C D
C D
K CP
K CP
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
HIGH
10 U.L.
LOADING (Note a)
J
Q
J
Q
Q 2
Q 2
5 (2.5) U.L.
0.25 U.L.
LOW
1.0 U.L.
1.0 U.L.
1.5 U.L.
C D
C D
K CP
K CP
Q
J
J
Q
Q 3
Q 3